Semiconductor structure with enhanced placeholder position margin
A semiconductor structure having improved placeholder position margin is provided. The semiconductor structure includes a backside source/drain contact structure contacting one source/drain region of a nanosheet transistor. The backside source/drain contact structure has a first portion and a second portion. The second portion of the backside source/drain contact structure, which is in direct contact with the source/drain region is confined by bottommost upper inner spacers, lower inner spacers and a semiconductor pedestal which vertically separates the bottommost inner spacers from the lower inner spacers.
1 . A semiconductor structure comprising:
a nanosheet transistor comprising a plurality of spaced apart and vertically stacked semiconductor channel material nanosheets, a gate structure wrapped around each semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets and a pair of source/drain regions;
upper inner spacers located between each vertically stacked pair of semiconductor channel material nanosheets of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets and beneath a bottommost semiconductor channel material nanosheet of the plurality of spaced apart and vertically stacked semiconductor channel material nanosheets;
lower inner spacers located beneath bottommost upper inner spacers, wherein each of the lower inner spacers is vertically separated from the bottommost upper inner spacers by a semiconductor pedestal; and
a backside source/drain contact structure contacting a first source/drain region of the pair of source/drain regions, wherein the backside source/drain contact structure has a first portion and a second portion, wherein the second portion of the backside source/drain contact structure is confined by the bottommost upper inner spacers, the lower inner spacers and the semiconductor pedestal.
2 . The semiconductor structure of claim 1 , wherein the first portion has a first critical dimension, and the second portion has a second critical dimension, wherein the second critical dimension is less than the first critical dimension.
3 . The semiconductor structure of claim 1 , further comprising a protective liner separating the second portion of the backside source/drain contact structure from the bottommost upper inner spacers, the lower inner spacers and the semiconductor pedestal.
4 . The semiconductor structure of claim 3 , wherein the protective liner contacts a surface of the first source/drain region that is in contact with the backside source/drain contact structure.
5 . The semiconductor structure of claim 1 , wherein a second source/drain region of the pair of source/drain regions is located on a semiconductor buffer layer.
6 . The semiconductor structure of claim 5 , wherein the semiconductor buffer layer is located on a surface of a backside source/drain contact placeholder structure.
7 . The semiconductor structure of claim 6 , further comprising a protective liner located on a sidewall of the semiconductor buffer layer and a sidewall of the backside source/drain contact placeholder structure, wherein the protective liner separates the semiconductor buffer layer and the backside source/drain contact placeholder structure from the lower inner spacers.
8 . The semiconductor structure of claim 7 , wherein the protective liner contacts a surface of the second source/drain region of the pair of source/drain regions.
9 . The semiconductor structure of claim 7 , wherein one of the semiconductor pedestals contacts a sidewall of the second source/drain region.
10 . The semiconductor structure of claim 5 , wherein the second source/drain region of the pair of source/drain regions has a vertical height that differs from a vertical height of the first source/drain region that contacts the backside source/drain contact structure.
11 . The semiconductor structure of claim 5 , further comprising a frontside source/drain contact structure contacting the second source/drain region of the pair of source/drain regions.
12 . The semiconductor structure of claim 11 , further comprising a frontside back-end-of-the-line (BEOL) structure contacting the frontside source/drain contact structure.
13 . The semiconductor structure of claim 12 , further comprising a frontside gate contact structure having a first surface contacting a gate electrode of the gate structure of the nanosheet transistor and a second surface opposite the first surface that contacts the frontside BEOL structure.
14 . The semiconductor structure of claim 1 , further comprising a backside interconnect structure contacting a surface of the backside source/drain contact structure.
15 . The semiconductor structure of claim 1 , wherein the semiconductor pedestal has a width that is less than a width of the upper inner spacers and a width of the lower inner spacers.
16 . The semiconductor structure of claim 1 , further comprising a backside interlayer dielectric (ILD) layer located beneath the nanosheet transistor and surrounding the backside source/drain contact structure.
17 . The semiconductor structure of claim 16 , wherein the backside ILD layer contacts sidewalls of both the semiconductor pedestal and the lower inner spacers.
18 . The semiconductor structure of claim 17 , wherein the backside ILD layer further contacts surfaces of both the bottommost upper inner spacers and a bottommost portion of the gate structure.
19 . The semiconductor structure of claim 1 , further comprising a shallow trench isolation structure located adjacent to the backside source/drain contact structure.
20 . The semiconductor structure of claim 19 , further comprising a backside source/drain contact placeholder structure laterally adjacent to the shallow trench isolation structure, wherein a semiconductor buffer layer is located on the backside source/drain contact placeholder structure and a second source/drain region of the pair of source/drain regions is located on the semiconductor buffer layer.