Logic device and manufacturing method thereof
A logic device includes a substrate; at least one first insulating layer on the substrate; a second insulating layer on the at least one first insulating layer; and a capacitor portion in the at least one first insulating layer and the second insulating layer, wherein the at least one first insulating layer includes a plurality of through-holes, the capacitor portion includes a capacitor structure including a lower electrode, a dielectric film, and an upper electrode, and the capacitor structure continuously extends along the inside of the plurality of through-holes and along an upper surface of the at least one first insulating layer around the plurality of through-holes.
1 . A logic device, comprising:
a substrate;
at least one first insulating layer on the substrate, the at least one first insulating layer including a plurality of through-holes therein;
a second insulating layer on the at least one first insulating layer;
wires in the at least one first insulating layer and the second insulating layer; and
a capacitor portion in the at least one first insulating layer and the second insulating layer, the capacitor portion including a capacitor structure with a lower electrode, a dielectric film, and an upper electrode, and the capacitor structure continuously extending inside the plurality of through-holes of the at least one first insulating layer and along an upper surface of the at least one first insulating layer around each of the plurality of through-holes,
wherein a ratio of a width of each of the plurality of through-holes to a width of each of the wires is 1:5 to 1:10.
2 . The logic device as claimed in claim 1 , wherein:
the lower electrode conformally extends inside the plurality of through-holes and along the upper surface of the at least one first insulating layer around each of the plurality of through-holes,
the dielectric film conformally extends along the lower electrode, and
the upper electrode conformally extends along the dielectric film.
3 . The logic device as claimed in claim 1 , wherein the capacitor portion further includes an interconnect member on the capacitor structure, the interconnect member including:
a first area having a plurality of filling plugs filling the plurality of through-holes on the capacitor structure, and
a second area having a plate member electrically connecting the plurality of filling plugs.
4 . The logic device as claimed in claim 3 , wherein the capacitor portion further includes a lower plate layer and an upper plate layer.
5 . The logic device as claimed in claim 4 , wherein:
the capacitor structure is on the lower plate layer, and
the upper plate layer is on the interconnect member.
6 . The logic device as claimed in claim 1 , wherein the lower electrode and the upper electrode include TiN.
7 . The logic device as claimed in claim 1 , wherein the dielectric film includes at least one of Zr oxide, Al oxide, and Ti oxide.
8 . A logic device, comprising:
a substrate;
at least one first insulating layer on the substrate, the at least one first insulating layer including a plurality of through-holes;
a second insulating layer on the at least one first insulating layer;
wires in the at least one first insulating layer and the second insulating layer; and
a capacitor portion in the at least one first insulating layer and the second insulating layer, the capacitor portion including:
a lower plate layer, a first portion of the wires being electrically connected to the lower plate layer,
a capacitor structure on the lower plate layer, the capacitor structure continuously extending along an upper surface of the lower plate layer, an inner surface of the plurality of through-holes, and an upper surface of the at least one first insulating layer around each of the plurality of through-holes,
an interconnect member on the capacitor structure, and
an upper plate layer on the interconnect member, a second portion of the wires being electrically connected to the upper plate layer,
wherein a ratio of a width of each of the plurality of through-holes to a width of each of the wires is 1:5 to 1:10.
9 . The logic device as claimed in claim 8 , wherein the lower plate layer and the upper plate layer include TiN.
10 . The logic device as claimed in claim 8 , wherein the interconnect member includes Al.
11 . The logic device as claimed in claim 8 , further comprising an etch-stop layer between the capacitor structure and the upper surface of the at least one first insulating layer around each of the plurality of through-holes.
12 . The logic device as claimed in claim 11 , wherein the etch-stop layer includes SiN.
13 . The logic device as claimed in claim 8 , wherein a ratio of a width of each of the plurality of through-holes to a width of the capacitor structure is 4:1 to 12:1.
14 . The logic device as claimed in claim 8 , wherein the capacitor portion is included in a back end of line.
15 . A manufacturing method of a logic device, the method comprising:
forming a lower plate layer and a first insulating layer on a substrate, such that the lower plate layer is between the substrate and the first insulating layer;
forming a plurality of wires in the first insulating layer;
forming a plurality of through-holes in the first insulating layer to expose the lower plate layer;
forming a capacitor structure in the plurality of through-holes of the first insulating layer, such that the capacitor structure continuously extends along an upper surface of the lower plate layer exposed by the plurality of through-holes, along inner surfaces of the plurality of through-holes, and an upper surface of the first insulating layer;
forming a plurality of filling plugs filling the capacitor structure in the plurality of through-holes, and depositing a plate member connecting the plurality of filling plugs on the plurality of filling plugs;
depositing an upper plate layer on the plate member;
etching the capacitor structure, the plate member, and the upper plate layer in an area in which the plurality of wires are formed; and
forming a first wire connected to the upper plate layer and a second wire connected to the lower plate layer.
16 . The manufacturing method of the logic device as claimed in claim 15 , wherein forming the first wire connected to the upper plate layer and the second wire connected to the lower plate layer includes forming each of the first wire and the second wire by a single damascene process.
17 . The manufacturing method of the logic device as claimed in claim 15 , wherein forming the first wire connected to the upper plate layer and the second wire connected to the lower plate layer includes forming the first wire and the second wire by a dual damascene process.
18 . The manufacturing method of the logic device as claimed in claim 15 , wherein forming the plurality of wires is performed by a dual damascene process.