Photonic passive delay lines with reduced parasitic losses
Various embodiments disclosed herein describe photonic passive delay lines that have a waveguide wound into a plurality of straight segments and bends. The photonic passive delay lines are configured to reduce losses from parasitic modes of light generated at the bends. Embodiments of the photonic passive delay lines vary the dimensions of the straight segments to provide different amounts of dephasing between a mode of input light received by the photonic passive delay line and one or more parasitic modes.
1 . A photonic integrated circuit comprising:
a photonic passive delay line configured to receive input light having an input mode and an input wavelength within a target wavelength range, the photonic passive delay line comprising:
a waveguide comprising:
an input segment;
an output segment;
a plurality of bends positioned between the input segment and the output segment along a length of the waveguide; and
a plurality of straight segments positioned between the input segment and the output segment along the length of the waveguide, wherein:
each straight segment of the plurality of straight segments is positioned between a corresponding pair of bends of the plurality of bends;
each straight segment of the plurality of straight segments comprises:
a first set of regions having a first aggregate length and a first waveguide width; and
a second set of regions having a second aggregate length and a second waveguide width larger than the first waveguide width; and
the first aggregate length of each straight segment of the plurality of straight segments is different and configured to dephase a parasitic mode.
2 . The photonic integrated circuit of claim 1 , wherein:
the waveguide comprises a turn segment that changes a winding direction of the waveguide and is positioned between the input segment and the output segment along the length of the waveguide.
3 . The photonic integrated circuit of claim 2 , wherein:
the plurality of straight segments is positioned between the input segment and the turn segment.
4 . The photonic integrated circuit of claim 1 , wherein:
for each straight segment of the plurality of straight segments:
the first set of regions comprises:
a first end region connected to a first corresponding bend; and
a second end region connected to a second corresponding bend immediately adjacent the first corresponding bend; and
the second set of regions comprises an intermediate region positioned between the first end region and the second end region along the length of the waveguide.
5 . The photonic integrated circuit of claim 1 , wherein:
the first waveguide width is less than 2 microns; and
the second waveguide width is greater than 2 microns.
6 . The photonic integrated circuit of claim 1 , wherein:
the plurality of straight segments is configured such that, for each wavelength within the target wavelength range and a parasitic mode:
at least one pair of immediately adjacent straight segments of the plurality of straight segments has a first aggregate length change that is greater than 0.4 effective dephasing lengths.
7 . The photonic integrated circuit of claim 6 , wherein:
the target wavelength range spans at least 500 nanometers.
8 . The photonic integrated circuit of claim 6 , wherein:
the input mode has a first polarization direction; and
the parasitic mode has a second polarization direction perpendicular to the first polarization direction.
9 . An optical system comprising:
a light source unit configured to generate output light at a set of wavelengths in a target wavelength range; the set of wavelengths includes a maximum wavelength of the target wavelength range and a minimum wavelength of the target wavelength range; and
a photonic integrated circuit comprising a photonic passive delay line; wherein:
the photonic passive delay line is optically connected to the light source unit to receive the output light as input light having an input mode;
the photonic passive delay line comprises:
a waveguide comprising:
an input segment;
an output segment;
a plurality of bends positioned between the input segment and the output segment along a length of the waveguide; and
a plurality of straight segments positioned between the input segment and the output segment along the length of the waveguide such that each straight segment of the plurality of straight segments is positioned between a corresponding pair of bends of the plurality of bends; and
the plurality of straight segments is configured such that, for each wavelength in the set of wavelengths, the plurality of straight segments has a distribution of effective dephasing lengths for a parasitic mode that spans at least 0.3 effective dephasing lengths.
10 . The optical system of claim 9 , wherein:
the light source unit is integrated into the photonic integrated circuit.
11 . The optical system of claim 9 , wherein:
the input mode has a first polarization direction; and
the parasitic mode has a second polarization direction perpendicular to the first polarization direction.
12 . The optical system of claim 9 , wherein:
the maximum wavelength and the minimum wavelength span at least 500 nanometers.
13 . The optical system of claim 12 , wherein:
the maximum wavelength and the minimum wavelength span at least 1000 nanometers.
14 . The optical system of claim 9 , wherein:
each straight segment of the plurality of straight segments comprises:
a first set of regions having a first waveguide width; and
a second set of regions having a second waveguide width larger than the first waveguide width.
15 . The optical system of claim 14 , wherein:
the first waveguide width is less than 2 microns; and
the second waveguide width is greater than 2 microns.
16 . A photonic integrated circuit comprising:
a photonic passive delay line configured to receive input light having an input mode and an input wavelength within a target wavelength range, the photonic passive delay line comprising:
a waveguide comprising:
an input segment;
an output segment;
a plurality of bends positioned between the input segment and the output segment along a length of the waveguide; and
a plurality of straight segments positioned between the input segment and the output segment along the length of the waveguide such that each straight segment of the plurality of straight segments is positioned between a corresponding pair of bends of the plurality of bends; wherein:
the plurality of straight segments is configured such that, for each wavelength within the target wavelength range and a parasitic mode, at least one pair of immediately adjacent straight segments of the plurality of straight segments has an effective dephasing length change that is greater than 0.4 effective dephasing lengths.
17 . The photonic integrated circuit of claim 16 , wherein:
the target wavelength range spans at least 500 nanometers.
18 . The photonic integrated circuit of claim 17 , wherein:
the target wavelength range spans at least 1000 nanometers.
19 . The photonic integrated circuit of claim 16 , wherein:
the input mode has a first polarization direction; and
the parasitic mode has a second polarization direction perpendicular to the first polarization direction.
20 . The photonic integrated circuit of claim 16 , wherein:
the waveguide comprises a turn segment that changes a winding direction of the waveguide and is positioned between the input segment and the output segment along the length of the waveguide.