Flash memory controller and associated memory device and control method
A flash memory controller is arranged to access a flash memory module, and includes a transmission interface circuit a buffer memory, and a microprocessor. The transmission interface circuit is coupled to a host device, wherein the transmission interface circuit includes a command processing circuit, and the command processing circuit is arranged to: receive a command from the host device; utilize multiple check items to check the command to generate at least one check result; and convert the command to generate a converted command of a specific format, wherein the converted command comprises an error state field for recording the at least one check result. The buffer memory is arranged to store the converted command. The microprocessor is arranged to read the converted command from the buffer memory, and access the flash memory module according to the converted command.
1. A flash memory controller, arranged to access a flash memory module, comprising:
a transmission interface circuit, coupled to a host device, wherein the transmission interface circuit comprises a command processing circuit, and the command processing circuit is arranged to:
receive a command from the host device;
utilize multiple check items to check the command to generate at least one check result; and
convert the command to generate a converted command of a specific format, wherein the converted command comprises an error state field for recording the at least one check result;
a buffer memory, arranged to store the converted command; and
a microprocessor, arranged to read the converted command from the buffer memory, and access the flash memory module according to the converted command;
wherein the converted command further comprises a logical unit number (LUN), a logical block address (LBA), and a transfer length;
wherein the converted command further comprises an operation code, and the operation code is arranged to indicate whether the command corresponding to the converted command is a read command of a first format, a read command of a second format, a write command of the first format, or a write command of the second format.
2. The flash memory controller of claim 1 , wherein in response to the at least one check result of the converted command indicating there is an error in the command, the microprocessor generates a response signal to the host device according to an error state of the at least one check result in the converted command.
3. The flash memory controller of claim 1 , wherein the at least one check result is multiple check results, the multiple check results correspond to the multiple check items, respectively, and each of the multiple check results indicates whether the command conforms to a corresponding check item.
4. The flash memory controller of claim 1 , wherein the converted command further comprises a label, and the label is arranged to indicate whether the converted command is a read command or a write command.
5. The flash memory controller of claim 1 , wherein the converted command further comprises a response setting, and the response setting is arranged to set that, in response to the command being stored in the buffer memory or the microprocessor successfully accessing the flash memory module according to the converted command, a response message is sent to the host device to notify that the command is received successfully.
6. The flash memory controller of claim 1 , wherein the converted command further comprises a group number, and the group number is arranged to set that a single-level cell (SLC) method, a multi-level cell (MLC) method, or a triple-level cell (TLC) method is utilized to perform a read/write operation upon the flash memory module.
7. The flash memory controller of claim 1 , wherein the converted command further comprises a memory slot index value, and the memory slot index value is arranged to indicate an address of the converted command within the buffer memory.
8. The flash memory controller of claim 1 , wherein operations of the command processing circuit are implemented by a hardware circuit, and generating the converted command of the specific format by converting the command through the command processing circuit does not involve operations of the microprocessor.
9. A memory device, comprising:
a flash memory module; and
a flash memory controller, arranged to access the flash memory module, comprising:
a transmission interface circuit, coupled to a host device, wherein the transmission interface circuit comprises a command processing circuit, and the command processing circuit is arranged to:
receive a command from the host device;
utilize multiple check items to check the command to generate at least one check result; and
convert the command to generate a converted command of a specific format, wherein the converted command comprises an error state field for recording the at least one check result;
a buffer memory, arranged to store the converted command; and
a microprocessor, arranged to read the converted command from the buffer memory, and access the flash memory module according to the converted command;
wherein the converted command further comprises a logical unit number (LUN), a logical block address (LBA), and a transfer length;
wherein the converted command further comprises an operation code, and the operation code is arranged to indicate whether the command corresponding to the converted command is a read command of a first format, a read command of a second format, a write command of the first format, or a write command of the second format.
10. A control method of a flash memory controller comprising:
receiving a command from a host device;
utilizing multiple check items to check the command to generate at least one check result, and converting the command to generate a converted command of a specific format, wherein the converted command comprises an error state field for recording the at least one check result;
storing the converted command in a buffer memory; and
reading the converted command from the buffer memory, and accessing the flash memory module according to the converted command;
wherein the converted command further comprises a logical unit number (LUN), a logical block address (LBA), and a transfer length;
wherein the converted command further comprises an operation code, and the operation code is arranged to indicate whether the command corresponding to the converted command is a read command of a first format, a read command of a second format, a write command of the first format, or a write command of the second format.
11. The control method of claim 10 , further comprising:
in response to the at least one check result of the converted command indicating there is an error in the command, generating a response signal to the host device according to an error state of the at least one check result in the converted command.
12. The control method of claim 10 , wherein the at least one check result is multiple check results, the multiple check results correspond to the multiple check items, respectively, and each of the multiple check results indicates whether the command conforms to a corresponding check item.
13. The control method of claim 10 , wherein the converted command further comprises a label, and the label is arranged to indicate whether the converted command is a read command or a write command.
14. The control method of claim 10 , wherein the converted command further comprises a response setting, and the response setting is arranged to set that, in response to the command being stored in the buffer memory or the microprocessor successfully accessing the flash memory module according to the converted command, a response message is sent to the host device to notify that the command is received successfully.
15. The control method of claim 10 , wherein the converted command further comprises a group number, and the group number is arranged to set that a single-level cell (SLC) method, a multi-level cell (MLC) method, or a triple-level cell (TLC) method is utilized to perform a read/write operation upon the flash memory module.
16. The control method of claim 10 , wherein the converted command further comprises a memory slot index value, and the memory slot index value is arranged to indicate an address of the converted command within the buffer memory.
17. The flash memory controller of claim 1 , wherein both the command and the converted command are stored in the buffer memory, and the flash memory controller selectively operates in a first mode and a second mode; and under the first mode, the microprocessor only reads the converted command from the buffer memory without executing the command; and under the second mode, the microprocessor only reads the command from the buffer memory.
18. The memory device of claim 9 , wherein both the command and the converted command are stored in the buffer memory, and the flash memory controller selectively operates in a first mode and a second mode; and under the first mode, the microprocessor only reads the converted command from the buffer memory without executing the command; and under the second mode, the microprocessor only reads the command from the buffer memory.
19. The control method of claim 10 , wherein both the command and the converted command are stored in the buffer memory, and the control method further comprises:
selectively operating in a first mode and a second mode;
under the first mode, only reading the converted command from the buffer memory without executing the command; and
under the second mode, only reading the command from the buffer memory.