Temperature sensor circuits for integrated circuit devices
An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.
1. A method, comprising:
providing a temperature sensor circuit in an integrated circuit device, the temperature sensor circuit including an insulated gate field effect transistor (IGFET) including at least three channels disposed in a first direction and are substantially aligned in a second direction substantially perpendicular to the first direction and substantially surrounded by a contiguous control gate structure, each channel provides a controllable impedance path between a commonly connected source terminal and a commonly connected drain terminal; and
providing at least one temperature signal with the temperature sensor circuit, the at least one temperature signal indicates a temperature window in which the integrated circuit device is operating and the control gate structure operates as a control gate for commonly selecting between a high impedance state and a low impedance state for each of the controllable impedance paths.
2. The method of claim 1 , wherein:
the insulated gate field effect transistor (IGFET) including at least three channels disposed in the first direction and are substantially aligned in the second direction substantially perpendicular to the first direction and substantially surrounded by the contiguous control gate structure that has a gate length of less than about 10 nm.
3. The method of claim 1 , wherein:
the insulated gate field effect transistor (IGFET) including at least three channels disposed in the first direction and are substantially aligned in the second direction substantially perpendicular to the first direction and substantially surrounded by the contiguous control gate structure that has a gate length of less than about 6 nm.
4. The method of claim 1 , further including:
providing a temperature dependent reference potential with a reference generator circuit included in the temperature sensor circuit, the reference generator circuit includes the IGFET.
5. The method of claim 4 , wherein:
the insulated gate field effect transistor (IGFET) including at least three channels disposed in the first direction and are substantially aligned in the second direction substantially perpendicular to the first direction and substantially surrounded by the contiguous control gate structure that has a gate length of less than about 10 nm.
6. The method of claim 5 wherein:
the insulated gate field effect transistor (IGFET) including at least three channels disposed in the first direction and are substantially aligned in the second direction substantially perpendicular to the first direction and substantially surrounded by the contiguous control gate structure that has a gate length of less than about 6 nm.
7. The method of claim 5 , further including:
providing an essentially temperature independent reference potential with the reference generator circuit.
8. The method of claim 1 , further including:
providing a refresh control circuit in the integrated circuit device, the refresh control circuit coupled to receive the at least one temperature signal; and
setting a refresh rate with the refresh control circuit in response to the at least one temperature signal wherein
the integrated circuit device is a dynamic random access memory device.
9. The method of claim 8 , wherein:
the insulated gate field effect transistor (IGFET) including at least three channels disposed in the first direction and are substantially aligned in the second direction substantially perpendicular to the first direction and substantially surrounded by the contiguous control gate structure that has a gate length of less than about 10 nm.
10. The method of claim 9 , wherein:
the insulated gate field effect transistor (IGFET) including at least three channels disposed in the first direction and are substantially aligned in the second direction substantially perpendicular to the first direction and substantially surrounded by the contiguous control gate structure that has a gate length of less than about 6 nm.
11. The method of claim 1 , further including:
providing an assist control circuit in the integrated circuit device, the assist control circuit coupled to receive the at least one temperature signal; and
by operation of the assist control circuit, enabling and disabling an assist circuit in response to the at least one temperature signal, the assist circuit assists a data transfer operation of static random access memory cells formed on the integrated circuit device.
12. The method of claim 11 , wherein:
the insulated gate field effect transistor (IGFET) including at least three channels disposed in the first direction and are substantially aligned in the second direction substantially perpendicular to the first direction and substantially surrounded by the contiguous control gate structure that has a gate length of less than about 10 nm.
13. The method of claim 12 , wherein:
the insulated gate field effect transistor (IGFET) including at least three channels disposed in the first direction and are substantially aligned in the second direction substantially perpendicular to the first direction and substantially surrounded by the contiguous control gate structure that has a gate length of less than about 6 nm.
14. The method of claim 12 , wherein:
by operation of the assist control circuit, assisting a read operation of data from static random access memory cells formed on the integrated circuit device.
15. The method of claim 12 , wherein:
by operation of the assist control circuit, assisting a write operation of data to static random access memory cells formed on the integrated circuit device.
16. The method of claim 1 , further including:
providing a frequency control circuit in the integrated circuit device, the frequency control circuit coupled to receive the at least one temperature signal;
by operation of the frequency control circuit, setting a frequency of a clock signal in response to the at least one temperature signal; and
the integrated circuit device includes processor circuitry coupled to receive the clock signal.
17. The method of claim 16 , wherein:
the insulated gate field effect transistor (IGFET) including at least three channels disposed in the first direction and are substantially aligned in the second direction substantially perpendicular to the first direction and substantially surrounded by the contiguous control gate structure that has a gate length of less than about 10 nm.
18. The method of claim 17 , wherein:
the insulated gate field effect transistor (IGFET) including at least three channels disposed in the first direction and are substantially aligned in the second direction substantially perpendicular to the first direction and substantially surrounded by the contiguous control gate structure that has a gate length of less than about 6 nm.
19. The method of claim 1 , further including:
providing a power up circuit in the integrated circuit device;
by operation of the power up circuit, providing a power up signal having a power up logic level in response to detecting power received by the integrated circuit device; and
by operation of the temperature sensor circuit, providing a predetermined state to the at least one temperature signal in response to the power up signal.
20. The method of claim 1 , wherein:
the insulated gate field effect transistor (IGFET) including at least four channels disposed in the first direction and are substantially aligned in the second direction substantially perpendicular to the first direction and substantially surrounded by a contiguous control gate structure, the at least four channels are electrically connected to a common source region.