Semiconductor device with recessed gate and method for fabricating the same
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a first peripheral region and a second peripheral region; a plurality of recessed gates respectively including a recessed gate dielectric layer inwardly positioned in the first peripheral region and including a U-shaped cross-sectional profile, a recessed gate bottom conductive layer positioned on the recessed gate dielectric layer and including a valley-shaped cross-sectional profile, resulting in a first valley, a recessed gate top conductive layer conformally positioned on the first valley of the recessed gate bottom conductive layer, and a recessed gate capping layer positioned on the recessed gate top conductive layer; and a peripheral gate structure positioned on the second peripheral region. An element density of the first peripheral region is greater than an element density of the second peripheral region.
1 . A semiconductor device, comprising:
a substrate comprising a first peripheral region and a second peripheral region;
a plurality of recessed gates respectively comprising:
a recessed gate dielectric layer inwardly positioned in the first peripheral region and comprising a U-shaped cross-sectional profile;
a recessed gate bottom conductive layer positioned on the recessed gate dielectric layer and comprising a valley-shaped cross-sectional profile, resulting in a first valley;
a recessed gate top conductive layer conformally positioned on the first valley of the recessed gate bottom conductive layer; and
a recessed gate capping layer positioned on the recessed gate top conductive layer; and
a peripheral gate structure positioned on the second peripheral region;
wherein an element density of the first peripheral region is greater than an element density of the second peripheral region.
2 . The semiconductor device of claim 1 , wherein the peripheral gate structure comprises:
a gate dielectric layer positioned on the second peripheral region;
a gate bottom conductive layer positioned on the gate dielectric layer;
a gate top conductive layer positioned on the gate bottom conductive layer; and
a gate capping layer positioned on the gate top conductive layer.
3 . The semiconductor device of claim 2 , wherein a width of the gate dielectric layer is greater than a width of the recessed gate dielectric layer.
4 . The semiconductor device of claim 3 , wherein the gate dielectric layer and the recessed gate dielectric layer comprise the same material.
5 . The semiconductor device of claim 3 , wherein the gate bottom conductive layer and the recessed gate bottom conductive layer comprise the same material.
6 . The semiconductor device of claim 3 , wherein the gate top conductive layer and the recessed gate top conductive layer comprise the same material.
7 . The semiconductor device of claim 3 , wherein the gate capping layer and the recessed gate capping layer comprise the same material.