Microprocessor with branch target buffer whose entries include fetch block hotness counters used for selective filtering of macro-op cache allocations
A microprocessor includes execution units that execute macro-operations (MOPs), a decode unit that decodes architectural instructions into MOPs, an instruction fetch unit (IFU) having an instruction cache that caches architectural instructions and a macro-operation cache (MOC) that caches MOPs into which the architectural instructions are decoded. A prediction unit (PRU) predicts a series of fetch blocks (FBs) in a program instruction stream to be fetched by the IFU from the MOC if hit or from the instruction cache otherwise. A branch target buffer (BTB) caches information about previously fetched and decoded FBs. A counter of each BTB entry is incremented when the entry predicts the associated FB is present again. For each FB in the series, the PRU indicates whether the counter has exceeded a threshold for use deciding whether to allocate the MOPs into the MOC in response to an instance of decoding the instructions into the MOPs.
1. A microprocessor, comprising:
execution units configured to execute macro-operations (MOPs);
a decode unit that decodes architectural instructions into MOPs;
an instruction fetch unit (IFU) comprising:
an instruction cache configured to cache architectural instructions fetched from system memory; and
a macro-operation cache (MOC) configured to cache MOPs into which the architectural instructions are decoded;
wherein the IFU is configured to detect whether MOPs into which architectural instructions of a fetch block (FB) have been decoded are present in the MOC and, if so, fetch the present one or more MOPs from the MOC for execution by the execution units rather than fetching the one or more architectural instructions from the instruction cache; and
a prediction unit (PRU) configured to predict a series of FBs in a program instruction stream to be fetched by the IFU, wherein the PRU comprises:
a branch target buffer (BTB) configured to cache information about previously fetched and decoded FBs in the program instruction stream, wherein each entry of the BTB is associated with a FB and comprises:
a counter that is incremented when the BTB entry is hit upon and used as a prediction that the associated FB is present again in the program instruction stream;
wherein the PRU is configured to, for each FB in the series, generate a true value on an indicator when the counter associated with the FB has exceeded a threshold; and
wherein the microprocessor is configured to, for each FB in the series, use the indicator associated with the FB in a filtering manner to decide whether or not to allocate the MOPs of the FB into the MOC in response to an instance of the decode unit decoding the architectural instructions of the FB into the MOPs of the FB.
2. The microprocessor of claim 1 ,
wherein the microprocessor is configured to decide to allocate the MOPs of the FB into the MOC only when the indicator is true.
3. The microprocessor of claim 1 ,
wherein the threshold is configurable by software executing on the microprocessor.
4. The microprocessor of claim 1 ,
wherein the indicator is provided from the PRU through the IFU to the decode unit for use by the decode unit to decide whether or not to allocate the MOPs of the FB into the MOC.
5. The microprocessor of claim 1 ,
wherein the decode unit comprises:
a simple decode unit configured to decode the architectural instructions of a FB into simple MOPs of the FB; and
a fusion engine configured to receive from the simple decode unit, in response to a true value on the indicator associated with the FB, the simple MOPs of the FB and to further fuse, when possible, the received simple MOPs into fewer and/or more complex MOPs than the received simple MOPs.
6. The microprocessor of claim 5 ,
wherein in response to detection that the counter associated with the FB has exceeded the threshold, the PRU sends a request to the fusion engine to further fuse the received simple MOPs into the complex MOPs for allocation into the MOC.
7. The microprocessor of claim 1 ,
wherein a MOP may be a result of a fusion of two or more architectural instructions.
8. The microprocessor of claim 1 ,
wherein a MOP may include more source operands and/or perform more arithmetical/logical operations than an architectural instruction.
9. The microprocessor of claim 1 ,
wherein each BTB entry further comprises:
a length of the associated FB; and
a termination type from a list comprising: the FB is terminated by a conditional branch instruction, the FB is terminated by an unconditional branch instruction, the FB is terminated because the FB reached a maximum sequential FB length.
10. The microprocessor of claim 1 ,
wherein the MOC comprises entries arranged as a set associative cache having sets and ways, wherein each set of the MOC includes replacement information used to determine which way of the set to replace upon allocation into the set;
wherein the counter indicates a worthiness of the MOPs of the FB to be allocated into the MOC based on a history of the FB being present in the program instruction stream;
wherein, for each way of the set, the replacement information indicates an unworthiness of the way, relative to the other ways of the set, to remain in the MOC based on a history of the way being present in the program instruction stream since being allocated into the MOC; and
wherein the microprocessor is configured to allocate the MOPs of the FB into the MOC based on their worthiness indicated by the counter relative to the threshold and independent of the unworthiness of the way of the set being replaced.
11. The microprocessor of claim 1 ,
wherein the BTB is indexed and tagged using a predicted fetch block start address (FBSA) that is looked up in the BTB to determine whether a BTB hit occurs; and
wherein the MOC is also indexed and tagged using the predicted FBSA that is also looked up in the MOC to determine whether a MOC hit occurs indicating that the MOPs of the FB associated with the hit BTB entry are present in the MOC.
12. The microprocessor of claim 11 ,
wherein the FBSA is a virtual address.
13. The microprocessor of claim 11 ,
wherein the PRU is configured to provide to the IFU a fetch block descriptor (FBD) that includes the indicator and the FBSA.
14. The microprocessor of claim 1 ,
wherein the counter is incremented only if the associated FB predicted by the BTB is executed and committed.
15. A method, comprising:
in a microprocessor comprising:
execution units configured to execute macro-operations (MOPs);
a decode unit that decodes architectural instructions into MOPs;
an instruction fetch unit (IFU) comprising:
an instruction cache configured to cache architectural instructions fetched from system memory; and
a macro-operation cache (MOC) configured to cache MOPs into which the architectural instructions are decoded;
wherein the IFU is configured to detect whether MOPs into which architectural instructions of a fetch block (FB) have been decoded are present in the MOC and, if so, fetch the present one or more MOPs from the MOC for execution by the execution units rather than fetching the one or more architectural instructions from the instruction cache; and
a prediction unit (PRU) configured to predict a series of FBs in a program instruction stream to be fetched by the IFU, wherein the PRU comprises:
a branch target buffer (BTB) configured to cache information about previously fetched and decoded FBs in the program instruction stream, wherein each entry of the BTB is associated with a FB and comprises:
a counter that is incremented when the BTB entry is hit upon and used as a prediction that the associated FB is present again in the program instruction stream;
for each FB in the series:
generating, by the PRU, a true value on an indicator when the counter associated with the FB has exceeded a threshold; and
using the indicator associated with the FB in a filtering manner to decide whether or not to allocate the MOPs of the FB into the MOC in response to an instance of the decode unit decoding the architectural instructions of the FB into the MOPs of the FB.
16. The method of claim 15 ,
wherein the MOPs of the FB are allocated into the MOC only when the indicator is true.
17. The method of claim 15 ,
wherein the threshold is configurable by software executing on the microprocessor.
18. The method of claim 15 , further comprising:
providing the indicator from the PRU through the IFU to the decode unit for use by the decode unit to decide whether or not to allocate the MOPs of the FB into the MOC.
19. The method of claim 15 , further comprising:
wherein the decode unit comprises:
a simple decode unit; and
a fusion engine;
decoding, by the simple decode unit, the architectural instructions of a FB into simple MOPs of the FB;
providing, by the simple decode unit, the simple MOPs of the FB to the fusion engine in response to a true value on the indicator associated with the FB; and
further fusing, by the fusion engine when possible, the simple MOPs into fewer and/or more complex MOPs than the received simple MOPs.
20. The method of claim 19 , further comprising:
sending, by the PRU in response to detection that the counter associated with the FB has exceeded the threshold, a request to the fusion engine to further fuse the received simple MOPs into the complex MOPs for allocation into the MOC.
21. The method of claim 15 ,
wherein a MOP may be a result of a fusion of two or more architectural instructions.
22. The method of claim 15 ,
wherein a MOP may include more source operands and/or perform more arithmetical/logical operations than an architectural instruction.
23. The method of claim 15 ,
wherein each BTB entry further comprises:
a length of the associated FB; and
a termination type from a list comprising: the FB is terminated by a conditional branch instruction, the FB is terminated by an unconditional branch instruction, the FB is terminated because the FB reached a maximum sequential FB length.
24. The method of claim 15 , further comprising:
wherein the MOC comprises entries arranged as a set associative cache having sets and ways, wherein each set of the MOC includes replacement information used to determine which way of the set to replace upon allocation into the set;
wherein the counter indicates a worthiness of the MOPs of the FB to be allocated into the MOC based on a history of the FB being present in the program instruction stream;
wherein, for each way of the set, the replacement information indicates an unworthiness of the way, relative to the other ways of the set, to remain in the MOC based on a history of the way being present in the program instruction stream since being allocated into the MOC; and
allocating the MOPs of the FB into the MOC based on their worthiness indicated by the counter relative to the threshold and independent of the unworthiness of the way of the set being replaced.
25. The method of claim 15 ,
wherein the BTB is indexed and tagged using a predicted fetch block start address (FBSA) that is looked up in the BTB to determine whether a BTB hit occurs; and
wherein the MOC is also indexed and tagged using the predicted FBSA that is also looked up in the MOC to determine whether a MOC hit occurs indicating that the MOPs of the FB associated with the hit BTB entry are present in the MOC.
26. The method of claim 25 ,
wherein the FBSA is a virtual address.
27. The method of claim 25 , further comprising:
providing, by the PRU, to the IFU a fetch block descriptor (FBD) that includes the indicator and the FBSA.
28. The method of claim 15 ,
wherein the counter is incremented only if the associated FB is executed and committed.
29. A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring a microprocessor comprising:
execution units configured to execute macro-operations (MOPs);
a decode unit that decodes architectural instructions into MOPs;
an instruction fetch unit (IFU) comprising:
an instruction cache configured to cache architectural instructions fetched from system memory; and
a macro-operation cache (MOC) configured to cache MOPs into which the architectural instructions are decoded;
wherein the IFU is configured to detect whether MOPs into which architectural instructions of a fetch block (FB) have been decoded are present in the MOC and, if so, fetch the present one or more MOPs from the MOC for execution by the execution units rather than fetching the one or more architectural instructions from the instruction cache; and
a prediction unit (PRU) configured to predict a series of FBs in a program instruction stream to be fetched by the IFU, wherein the PRU comprises:
a branch target buffer (BTB) configured to cache information about previously fetched and decoded FBs in the program instruction stream, wherein each entry of the BTB is associated with a FB and comprises:
a counter that is incremented when the BTB entry is hit upon and used as a prediction that the associated FB is present again in the program instruction stream;
wherein the PRU is configured to, for each FB in the series, generate a true value on an indicator when the counter associated with the FB has exceeded a threshold; and
wherein the microprocessor is configured to, for each FB in the series, use the indicator associated with the FB in a filtering manner to decide whether or not to allocate the MOPs of the FB into the MOC in response to an instance of the decode unit decoding the architectural instructions of the FB into the MOPs of the FB.