Optimizing thread selection at fetch, select, and commit stages of processor core pipeline

1. An apparatus, comprising:

a buffer configured to store a plurality of instructions, each instruction of the plurality of instructions included in a corresponding thread of a plurality of threads; and

control circuitry configured to:

maintain a table of thread status data for the plurality of threads, wherein the table of thread status data includes at least a respective count value that indicates a number of instructions in the buffer for the corresponding thread, and a respective indicator that is asserted if the corresponding thread is in a particular mode due to a cache miss;

in response to a determination that a respective indicator for a particular thread is asserted, adjust the respective count value to decrease a selection priority for the particular thread;

select a given thread of the plurality of threads based on the respective count values;

fetch one or more associated instructions corresponding to the given thread from a memory; and

store the one or more associated instructions in the buffer.

2. The apparatus of claim 1 , wherein the control circuitry is further configured to select the given thread with a respective count value that is less than the respective count value corresponding to each remaining thread of the plurality of threads.

3. The apparatus of claim 1 , wherein the particular mode corresponds to a miss look ahead mode.

4. The apparatus of claim 1 , wherein to select the given thread of the plurality of threads based on the respective count values, the control circuitry is further configured to:

assign each thread to one of at least two groups based on the respective count value corresponding to each thread of the plurality of threads; and

select from a first group of the at least two groups, the given thread that has the longest time period since a previous selection.

5. The apparatus of claim 4 , wherein the control circuitry is further configured to, in response to a determination that no threads assigned to the first group are eligible for selection, select from a second group of the at least two groups, the given thread that has the longest time period since a previous selection.

6. The apparatus of claim 1 , wherein the control circuitry is further configured to:

assign each thread of the plurality of threads to one of at least two groups based on a determination if a critical instruction in the buffer is included in the corresponding thread;

select from a first group of the at least two groups, a different thread that has the longest time period since a previous selection, wherein the first group includes threads that include a critical instruction in the buffer; and

commit an instruction included in the different thread.

7. The apparatus of claim 1 , wherein the memory corresponds to an instruction cache and the buffer corresponds to a fetch buffer.

8. A method comprising:

storing, in a first buffer, a plurality of instructions each of which is included in a corresponding thread of a plurality of threads;

storing, by a control circuit, a table of thread status data for the plurality of threads, wherein the table of thread status data includes at least a respective count value that indicates a number of instructions in the first buffer for the corresponding thread, and a respective indicator that is asserted if the corresponding thread is in a particular mode due to a cache miss;

in response to a determination that a respective indicator for a particular thread is asserted, adjusting the respective count value to decrease a selection priority for the particular thread;

selecting a given thread of the plurality of threads based on the respective count values;

copying a particular instruction in the given thread from a second buffer; and

storing the particular instruction in the first buffer.

9. The method of claim 8 , wherein the respective count value corresponding to the given thread is less than the respective count value corresponding to each remaining thread of the plurality of threads.

10. The method of claim 8 , wherein the particular mode corresponds to a miss look ahead mode.

11. The method of claim 8 , wherein selecting the given thread of the plurality of threads based on the respective count values further comprises:

assigning each thread to one of at least two groups based on the respective count values corresponding to each thread of the plurality of threads; and

selecting from a first group of the at least two groups, the given thread that has the longest time period since a previous selection.

12. The method of claim 11 , further comprising, in response to determining that no threads assigned to the first group are eligible for selection, selecting from a second group of the at least two groups, the given thread that has the longest time period since a previous selection.

13. The method of claim 8 , wherein selecting the given thread further comprises:

assigning each thread of the plurality of threads to one of at least two groups based on a determination if a critical instruction in the first buffer is included in the corresponding thread;

selecting from a first group of the at least two groups, a different thread that has the longest time period since a previous selection, wherein the first group includes threads that include a critical instruction in the first buffer; and

committing an instruction included in the different thread.

14. The method of claim 8 , wherein the first buffer is a reorder buffer and the second buffer is a fetch buffer.

15. A system, comprising:

a first buffer configured to store a first plurality of instructions, each of which is included in a corresponding thread of a plurality of threads;

a second buffer configured to store a second plurality of instructions each of which is included in a corresponding thread of the plurality of threads; and

a control circuit configured to:

track a table of thread status data for the plurality of threads, wherein the table of thread status data includes at least a respective count value that indicates a number of instructions stored in the second buffer for the corresponding thread, and a respective indicator that is asserted if the corresponding thread is in a particular mode due to a cache miss;

in response to a determination that a respective indicator for a particular thread is asserted, adjust the respective count value to decrease a selection priority for the particular thread;

select a given thread of the plurality of threads based on the respective count values; and

fetch a particular instruction included in the given thread from the first buffer to the second buffer.

16. The system of claim 15 , wherein the control circuit is further configured to:

select a given thread of the plurality of threads based on a number of instructions stored in the first buffer that are included in the given thread;

fetch a particular instruction included in the given thread from a memory; and

store the particular instruction in the first buffer.

17. The system of claim 15 , wherein the particular mode corresponds to a miss look ahead mode.

18. The system of claim 15 , wherein to select the given thread of the plurality of threads, the control circuit is further configured to:

assign each thread to one of at least two groups based on the respective count values corresponding to each thread of the plurality of threads; and

select from a first group of the at least two groups, the given thread that has the longest time period since a previous selection.

19. The system of claim 15 , wherein to select a given thread of the plurality of threads, the control circuit is further configured to:

assign each thread of the plurality of threads to one of at least two groups based on a determination if a critical instruction in the second buffer is included in the corresponding thread;

select from a first group of the at least two groups, a different thread that has the longest time period since a previous selection, wherein the first group includes threads that include a critical instruction in the second buffer; and

commit an instruction included in the different thread.

20. The system of claim 16 , wherein the memory corresponds to an instruction cache the first buffer corresponds to a fetch buffer, and the second buffer corresponds to a pick queue.