IP Library › Granted Patent US 12,652,970
Granted Patent B2
US 12,652,970 · App. 18/242,423 · Granted Jun 9, 2026

Resistive switching in a RRAM device

Inventors: Hieu Nguyen (Dover, NJ); Ravi Teja Velpula (Colonia, NJ); Barsha Jain (Colonia, NJ)
Assignee: New Jersey Institute of Technology
H10N70/883H10B63/80H10N70/841
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Quick Facts
Patent No.
US 12,652,970
App. No.
18/242,423
Granted
Jun 9, 2026
Kind
B2
Abstract

A resistive random access memory (RRAM) device is provided, and includes a top electrode layer, a bottom electrode layer, and an insulating layer positioned between the top electrode layer and the bottom electrode layer. The insulating layer includes a SiN x layer.

Claims (30)

1 . A resistive random access memory (RRAM) device, comprising:

a top electrode layer;

a bottom electrode layer; and

an insulating layer positioned between the top electrode layer and the bottom electrode layer, the insulating layer including a SiN x layer;

wherein the insulating layer comprises a SiO 2 layer positioned below the SiN x layer.

2 . The RRAM device of claim 1 , wherein the RRAM device has a resistive switching current in a nA range.

3 . The RRAM device of claim 1 , wherein the top electrode layer includes a Pt layer positioned over a Ti layer.

4 . The RRAM device of claim 3 , wherein the Pt layer is about 100 nm thick.

5 . The RRAM device of claim 3 , wherein the Ti layer is about 10 nm thick.

6 . The RRAM device of claim 1 , wherein the bottom electrode layer includes a TiN layer positioned over a Ti layer.

7 . The RRAM device of claim 6 , wherein the TiN layer is about 100 nm thick.

8 . The RRAM device of claim 6 , wherein the Ti layer is about 10 nm thick.

9 . The RRAM device of claim 1 , comprising an F silica substrate, wherein the bottom electrode layer is positioned on the F silica substrate.

10 . The RRAM device of claim 1 , wherein the SiN x layer is about 5 nm thick.

11 . The RRAM device of claim 1 , wherein the SiO 2 layer is about 10 nm thick.

12 . The RRAM device of claim 1 , wherein the SiN x layer is positioned between the top electrode layer and the bottom electrode layer.

13 . The RRAM device of claim 1 , wherein the insulating layer is a resistive layer having a bilayer structure.

14 . A switching device, comprising:

a top electrode layer;

a bottom electrode layer; and

a resistive switching bilayer positioned between the top electrode layer and the bottom electrode layer;

wherein the resistive switching bilayer includes SiN x /SiO 2 .

15 . The switching device of claim 14 , wherein the switching device has a resistive switching current in the nA range.

16 . The switching device of claim 14 , wherein the resistive switching bilayer includes a SiN x layer positioned over a SiO 2 layer.

17 . The switching device of claim 14 , wherein:

the top electrode layer includes a Pt layer positioned over a Ti layer; and

the bottom electrode layer includes a TiN layer positioned over a Ti layer.

18 . A method of operating a resistive random access memory (RRAM) device, comprising:

applying an external voltage to the RRAM device, the RRAM device including (i) a top electrode layer, (ii) a bottom electrode layer, and (iii) an insulating layer positioned between the top electrode layer and the bottom electrode layer, the insulating layer including a SiN x layer and the insulating layer comprises a SiO 2 layer positioned below the SiN x layer;

wherein application of the external voltage to the RRAM device changes the resistance across the insulating layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: NGUYEN, HIEU; VELPULA, RAVI TEJA; JAIN, BARSHA
To: NEW JERSEY INSTITUTE OF TECHNOLOGY
Reel/Frame 066308/0488 →
Continuity (2)
Provisional Application 63410293 · Sep 27, 2022
Related Publication 20240107904A1 · Mar 28, 2024
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