High electron affinity dielectric layer to improve cycling
Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.
1. A memory cell, comprising:
a bottom electrode;
a top electrode overlying the bottom electrode; and
a dielectric stack comprising a plurality of dielectric layers stacked between the bottom and top electrodes,
wherein the plurality of dielectric layers comprises a first dielectric layer, a second dielectric layer, and a third dielectric layer,
the second dielectric layer is between the first and third dielectric layers, and
the first dielectric layer is a closest one of the plurality of dielectric layers to the bottom electrode and has a highest electron affinity amongst the plurality of dielectric layers.
2. The memory cell according to claim 1 , wherein the second dielectric layer has a different set of elements than the first dielectric layer.
3. The memory cell according to claim 1 , wherein the second dielectric layer has a same set of elements as the first dielectric layer and further has a different ratio of the elements than the first dielectric layer.
4. The memory cell according to claim 1 , wherein the dielectric stack consists of three dielectric layers.
5. The memory cell according to claim 1 , further comprising:
a cap layer overlying the dielectric stack, between the dielectric stack and the top electrode, wherein the cap layer has a higher affinity for oxygen than the top and bottom electrodes.
6. The memory cell according to claim 1 , wherein the second dielectric layer has an electron affinity between that of the first dielectric layer and that of the third dielectric layer.
7. The memory cell according to claim 1 , wherein the third dielectric layer has an electron affinity between that of the first dielectric layer and that of the second dielectric layer.
8. The memory cell according to claim 1 , further comprising:
a conductive filament in the dielectric stack, wherein the conductive filament comprises oxygen vacancies.
9. The memory cell according to claim 1 , further comprising:
a conductive filament in the dielectric stack, wherein the conductive filament comprises metal.
10. A memory device comprising a memory cell, wherein the memory cell comprises:
a bottom electrode;
a dielectric structure overlying the bottom electrode and comprising multiple different dielectric materials from top to bottom; and
a top electrode overlying the dielectric structure,
wherein the multiple different dielectric materials comprise at least three different dielectric materials, which comprise a first dielectric material at the bottom electrode,
the first dielectric material has a bottom conductive band edge that is lowest amongst the multiple different dielectric materials, and
a bottom conductive band edge of the dielectric structure steps up from the bottom electrode to a top surface of the dielectric structure.
11. The memory device according to claim 10 , wherein the memory cell further comprises:
a cap layer between and contacting the top electrode and the dielectric structure, wherein the cap layer is conductive and depends upon less energy to react with oxygen than the top electrode.
12. The memory device according to claim 10 , further comprising:
a conductive filament in the dielectric structure, wherein the conductive filament extends from the top surface of the dielectric structure towards a bottom surface of the dielectric structure and terminates before the bottom surface of the dielectric structure.
13. An integrated circuit (IC) chip comprising a memory cell, wherein the memory cell comprises:
a first electrode;
a second electrode overlying the first electrode; and
a plurality of dielectric layers stacked between the first and second electrodes,
wherein the plurality of dielectric layers comprise a first dielectric layer, a second dielectric layer overlying the first dielectric layer, and a third dielectric layer overlying the second dielectric layer,
the first dielectric layer is closest to the first electrode amongst the plurality of dielectric layers,
the second dielectric layer has a bandgap larger than a bandgap of the first dielectric layer, and
the third dielectric layer has a bandgap smaller than the bandgap of the second dielectric layer and larger than the bandgap of the first dielectric layer.
14. The IC chip according to claim 13 , wherein a top valence band edge of the first dielectric layer is highest amongst the plurality of dielectric layers.
15. The IC chip according to claim 13 , wherein a bottom conductive band edge of the first dielectric layer is closest to a fermi level of the first electrode amongst the plurality of dielectric layers.
16. The IC chip according to claim 13 , further comprising:
a metal cap layer between and directly contacting the second electrode and a topmost one of the plurality of dielectric layers, wherein the metal cap layer has a higher affinity for oxygen than the second electrode.
17. The IC chip according to claim 15 , further comprising:
a substrate;
a transistor over the substrate; and
an interconnect structure over and electrically coupled to the transistor,
wherein the memory cell is in the interconnect structure, and wherein the first electrode is electrically shorted to a source/drain region of the transistor by the interconnect structure.
18. The memory device according to claim 10 , wherein a top valence band edge of the dielectric structure steps down from the bottom electrode to the top surface of the dielectric structure.
19. The IC chip according to claim 13 , wherein the third dielectric layer has an electron affinity between that of the first dielectric layer and that of the second dielectric layer.
20. The IC chip according to claim 14 , wherein a top valence band edge of the third dielectric layer is between a top valance band edge of the second dielectric layer and the top valence band edge of the first dielectric layer.