IP Library › Granted Patent US 11,430,948
Granted Patent B2
US 11,430,948 · App. 16/641,588 · Granted Aug 30, 2022

Resistive random access memory device with switching multi-layer stack and methods of fabrication

Inventors: Timothy Glassman (Portland, OR); Dragos Seghete (Portland, OR); Nathan Strutt (Beaverton, OR); Namrata S. Asuri (Portland, OR); Oleg Golonzka (Beaverton, OR); Hiten Kothari (Hillsboro, OR); Matthew J. Andrus (Hillsboro, OR)
Assignee: INTEL CORPORATION
H01L45/08H01L27/2436H01L45/1233H01L45/1253H01L45/146H01L45/1625H01L45/1641H01L45/1675
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Quick Facts
Patent No.
US 11,430,948
App. No.
16/641,588
Granted
Aug 30, 2022
Kind
B2
Abstract

A memory device includes a bottom electrode above a substrate, a first switching layer on the bottom electrode, a second switching layer including aluminum on the first switching layer, an oxygen exchange layer on the second switching layer and a top electrode on the oxygen exchange layer. The presence of the second switching layer including aluminum on the first switching layer enables a reduction in electro-forming voltage of the memory device.

Claims (43)

1. A memory device, comprising:

a substrate;

a bottom electrode above the substrate;

a first switchable layer on the bottom electrode;

a second switchable layer comprising aluminum on the first switchable layer;

an oxygen exchange layer on the second switchable layer; and

a top electrode on the oxygen exchange layer;

wherein the bottom electrode, the first switchable layer, the second switchable layer, the oxygen exchange layer and the top electrode form a stack having a sidewall, and wherein the memory device further comprises a dielectric spacer film surrounding the sidewall of the stack and extending from a lowermost portion of the bottom electrode to an uppermost portion of the top electrode, and

wherein the first switchable layer has a thickness between 2 nm and 4 nm, wherein the second switchable layer has a thickness between 1 nm and 2 nm, and wherein the first switchable layer and the second switchable layer have a total combined thickness between 3 nm and 5 nm.

2. The memory device of claim 1 , wherein the first switchable layer comprises a metal and oxygen.

3. The memory device of claim 2 , wherein the first switchable layer comprises hafnium oxide, tantalum oxide, zirconium oxide, titanium oxide, or tungsten oxide.

4. The memory device of claim 3 , wherein the first switchable layer is sub-stoichiometric.

5. The memory device of claim 1 , wherein the second switchable layer comprises aluminum and oxygen.

6. The memory device claim 1 , wherein the first switchable layer and the oxygen exchange layer comprise a same metal.

7. A memory device, comprising:

a substrate;

a bottom electrode above the substrate, wherein the bottom electrode comprises one or more of titanium, tantalum, tungsten, ruthenium, and nitrogen;

a first switchable layer on the bottom electrode, wherein at least a portion of an interface between the bottom electrode and the first switchable layer is oxidized;

a second switchable layer comprising aluminum on the first switchable layer;

an oxygen exchange layer on the second switchable layer;

a top electrode on the oxygen exchange layer, wherein the second switchable layer, the oxygen exchange layer, and the top electrode form a stack having a sidewall; and

a dielectric spacer film on the sidewall of the stack and extending at least from a lowermost portion of the second switchable layer to an uppermost portion of the top electrode,

wherein the first switchable layer has a thickness between 2 nm and 4 nm, wherein the second switchable layer has a thickness between 1 nm and 2 nm, and wherein the first switchable layer and the second switchable layer have a total combined thickness between 3 nm and 5 nm.

8. The memory device of claim 1 , wherein the top electrode comprises titanium nitride, tantalum nitride, tungsten, or ruthenium.

9. The memory device of claim 1 , wherein the bottom electrode and the top electrode are a same material, the material comprising titanium nitride, tantalum nitride, tungsten, or ruthenium.

10. A IT-IR memory cell, comprising:

a resistive random access memory (RRAM) device including

a bottom electrode comprising a metal layer;

a first switchable layer on the bottom electrode, wherein at least a portion of an interface between the bottom electrode metal layer and the first switchable layer is oxidized;

a second switchable layer comprising Al 2 O 3 (aluminum oxide) on the first switchable layer;

an oxygen exchange layer on the second switchable layer; and

a top electrode on the oxygen exchange layer,

wherein the first switchable layer has a thickness of at least 2 nm, and wherein the second switchable layer has a thickness of at least 1 nm.

11. The IT-IR memory cell of claim 10 , wherein the first switchable layer comprises a metal and oxygen.

12. The IT-IR memory cell of claim 10 , wherein the first switchable layer comprises hafnium oxide, tantalum oxide, zirconium oxide, titanium oxide, or tungsten oxide.

13. The IT-IR memory cell of claim 10 , wherein the first switchable layer has a thickness between 2 nm and 4 nm, wherein the second switchable layer has a thickness between 1 nm and 2 nm, and wherein the first switchable layer and the second switchable layer have a total combined thickness between 3 nm and 5 nm.

14. The memory device of claim 7 , wherein the stack further includes the bottom electrode and the first switchable layer, and wherein the dielectric spacer film extends from a lowermost portion of the bottom electrode to the uppermost portion of the top electrode.

15. The memory device of claim 7 , wherein the first switchable layer comprises a metal and oxygen, and wherein the second switchable layer comprises aluminum and oxygen.

16. The memory device of claim 7 , wherein the first switchable layer and the oxygen exchange layer comprise a same metal.

17. The memory device of claim 7 , wherein one or both of the bottom electrode and the top electrode comprises titanium, tantalum, tungsten, or ruthenium.

18. The IT-IR memory cell of claim 10 , wherein the second switchable layer comprises graded concentration of oxygen, with a first concentration of oxygen within the second switchable layer near the first switchable layer, and a second concentration of oxygen within the second switchable layer near the oxygen exchange layer, wherein the first concentration is different from the second concentration.

19. The IT-IR memory cell of claim 18 , wherein the first concentration is higher than the second concentration.

20. The IT-IR memory cell of claim 10 , comprising a dielectric spacer film on a sidewall of the second switchable layer, on a sidewall of the oxygen exchange layer, and on a sidewall of the top electrode.

Continuity (1)
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