Granted Patent B2

US 12,593,488 · App. 18/245,451 · Granted Mar 31, 2026

Inventors: James G. Fiorenza (Carlisle, MA); Daniel Piedra (Somerville, MA)

Assignee: Analog Devices, Inc.

H10D64/251H01L23/3672H01L23/5226H01L23/5283H01L23/66H10D30/015H10D30/475H10D62/235H10D62/8503H10D64/511

Abstract

Claims (59)

1 . A semiconductor device comprising:

a first compound semiconductor device including:

a first semiconductor layer that includes a first barrier layer and a first channel layer, the first channel layer being comprised of a compound material having a Group 13 element and a Group 15 element; and

a first drain electrical contact, a first source electrical contact, and a first gate electrical contact disposed on the first channel layer; and

a second compound semiconductor device including:

a second semiconductor layer that includes a second barrier layer and a second channel layer, the second channel layer being comprised of the compound material having the Group 13 element and the Group 15 element; and

a second drain electrical contact, a second source electrical contact, and a second gate electrical contact disposed on the second channel layer; and

wherein the first compound semiconductor device and the second compound semiconductor device are coupled in a face-to-face arrangement such that a gap is present between the first gate electrical contact and the second gate electrical contact.

2 . The semiconductor device of claim 1 , wherein:

the gap is from about 5 nanometers to about 40 nanometers.

3 . The semiconductor device of claim 1 , wherein:

the first source electrical contact is coupled to the second source electrical contact by an amount of bonding material disposed between the first source electrical contact and the second source electrical contact; and

the first drain electrical contact is coupled to the second drain electrical contact by an additional amount of the bonding material disposed between the first drain electrical contact and the second drain electrical contact.

4 . The semiconductor device of claim 3 , wherein:

the bonding material includes at least one of aluminum germanium, copper, or gold;

the first gate electrical contact and the second gate electrical contact are disposed in a cavity; and

a gas is present in the cavity that includes nitrogen or argon.

5 . The semiconductor device of claim 1 , wherein:

the first compound semiconductor device includes a substrate coupled to the first barrier layer;

a metallic layer coupled to the substrate;

one or more thru vias disposed in the first semiconductor layer and the substrate; and

the one or more thru vias electrically connect the metallic layer to at least one of the first source electrical contact or the second source electrical contact.

6 . The semiconductor device of claim 5 , wherein:

the substrate includes silicon carbide (SiC); and

one or more interconnects are formed within the substrate.

7 . The semiconductor device of claim 1 , wherein:

the second compound semiconductor device includes an additional substrate coupled to the second barrier layer; and

one or more recessed regions are formed from the additional substrate, wherein the one or more recessed regions form one or more fins to dissipate heat produced during use of the semiconductor device.

8 . The semiconductor device of claim 1 , wherein the compound semiconductor device has a power density of at least about 8 Watts per millimeter gate width to about 12 Watts per mm gate width at frequencies from about 25 GHz to about 35 GHz.

9 . A process to produce a compound semiconductor device, the process comprising:

producing a first compound semiconductor device, the first compound semiconductor device including:

a first semiconductor layer that includes a first barrier layer and a first channel layer, the first channel layer being comprised of a compound material having a Group 13 element and a Group 15 element; and

a first drain electrical contact, a first source electrical contact, and a first gate electrical contact disposed on the first channel layer;

producing a second compound semiconductor device, the second compound semiconductor device including:

a second semiconductor layer that includes a second barrier layer and a second channel layer, the second channel layer being comprised of the compound material having the Group 13 element and the Group 15 element; and

a second drain electrical contact, a second source electrical contact, and a second gate electrical contact disposed on the second channel layer; and

coupling the first compound semiconductor device to the second compound semiconductor device in a face-to-face arrangement to produce the compound semiconductor device such that a gap is present between the first gate electrical contact and the second gate electrical contact.

10 . The process of claim 9 , comprising:

applying a bonding material to at least a portion of at least one of the first compound semiconductor device or the second compound semiconductor device to couple the first compound semiconductor device to the second compound semiconductor device.

11 . The process of claim 10 , wherein the bonding material includes at least one of aluminum germanium, copper, or gold.

12 . The process of claim 10 , comprising:

heating the bonding material to a temperature from about 375° C. to about 450° C. to produce a heated bonding material; and

wherein the first compound semiconductor device is coupled to the second compound semiconductor device using the heated bonding material.

13 . The process of claim 10 , wherein the bonding material is applied to at least one of the first drain electrical contact or the second drain electrical contact and the bonding material is applied to at least one of the first source electrical contact or the first drain electrical contact.

14 . The process of claim 10 , comprising:

performing one or more operations to activate one or more surfaces of at least one of the first compound semiconductor device or the second compound semiconductor device to couple the first compound semiconductor device to the second compound semiconductor device.

15 . The process of claim 14 , wherein the one or more surfaces are activated using a plasma activation process performed at temperatures no greater than 120° C. and using an oxygen-containing gas.

16 . The process of claim 15 , comprising:

heating the bonding material after performing the one or more operations to activate the one or more surfaces.

17 . The process of claim 9 , wherein the first compound semiconductor device includes a substrate that is coupled to the first semiconductor layer and the first-substrate is coupled to a carrier substrate by an additional bonding material, the additional bonding material including a polymeric bonding material.

18 . The process of claim 17 , comprising:

removing the carrier substrate;

performing a die cutting operation to produce a plurality of compound semiconductor devices, individual compound semiconductor devices including:

at least one first drain electrical contact of the first compound semiconductor device coupled to at least one second drain electrical contact of the second compound semiconductor device by an amount of bonding material;

at least one first source electrical contact of the first compound semiconductor device coupled to at least one second source electrical contact of the second compound semiconductor device by an additional amount of the bonding material; and

a cavity including at least one first gate electrical contact of the first compound semiconductor device and at least one second gate electrical contact of the second compound semiconductor device.

19 . The process of claim 9 , wherein:

the compound semiconductor device includes a cavity that includes the first gate electrical contact and the second gate electrical contact disposed in a face-to-face-arrangement.

20 . The process of claim 19 , wherein the cavity is filled with an inert gas.

Assignments (1)

Continuity (2)

References Cited (34)