Memory cell array unit
A memory cell array unit according to an embodiment of the present disclosure includes a microcontroller that performs reading and writing from and into a memory cell array using n-bit allocation memory cells on the basis of read/write control from a memory controller. When a defect is found in one of the n-bit allocation memory cells, the microcontroller writes n−1-bit write data excluding data of a least significant bit among n-bit write data into n−1-bit allocation memory cells excluding the defective allocation memory cell among the n-bit allocation memory cells.
1. A memory cell array unit comprising:
a memory cell array that includes a plurality of n-bit allocation memory cells, wherein
the memory cell array is configured to receive a control signal from a memory controller,
the control signal comprises n-bit data, and
the memory controller allocates the plurality of n-bit allocation memory cells to the n-bit data; and
a microcontroller configured to:
read and write the n-bit data from and into the memory cell array based on the control signal;
receive n-bit write data and control data from a host computer;
write n−1-bit write data into a plurality of n−1-bit allocation memory cells, wherein the n-bit write data includes n−1-bit write data;
determine a defect in the plurality of n-bit allocation memory cells based on the n-bit write data and the control data;
determine a defective allocation memory cell of the plurality of n-bit allocation memory cells based on the determined defect; and
exclude the defective allocation memory cell and first data, wherein
the n−1-bit write data includes the first data, and
the first data corresponds to a least significant bit of the n−1-bit write data.
2. The memory cell array unit according to claim 1 , wherein the microcontroller is further configured to determine the defect each time the microcontroller reads and writes the n-bit data from and into the memory cell array.
3. The memory cell array unit according to claim 2 , wherein the microcontroller is further configured to:
read n-bit read data from the plurality of n-bit allocation memory cells, wherein the n-bit read data comprises second data;
generate the n-bit data based on addition of 1-bit data to n−1-bit read data, wherein the 1-bit data corresponds to the least significant bit;
output the generated n-bit data to the memory controller based on the determined defect in the plurality of n-bit allocation memory cells; and
exclude the second data associated with a specific bit, wherein the specific bit corresponds to the defective allocation memory cell.
4. The memory cell array unit according to claim 3 , wherein the microcontroller is further configured to output the n-bit read data to the memory controller based on an absence of the defect.
5. The memory cell array unit according to claim 2 , wherein the microcontroller is further configured to write the n-bit write data into the plurality of n-bit allocation memory cells based on an absence of the defect.
6. The memory cell array unit according to claim 1 , wherein
the memory cell array further includes a plurality of a-bit error correction code (ECC) parity memory cells,
the memory controller allocates an a-bit ECC parity bit to the plurality of a-bit ECC parity memory cells, and
the microcontroller is further configured to:
generate n−1+a-bit first data based on the n−1-bit write data; and
write, into the plurality of n−1-bit allocation memory cells and the plurality of a-bit ECC parity memory cells, the n−1+a-bit first data.
7. The memory cell array unit according to claim 6 , wherein the microcontroller is further configured to:
generate n+a−1-bit read data based on the determined defect in the plurality of n-bit allocation memory cells;
generate the n-bit data based on the generated n+a−1-bit read data; and
output the generated n-bit data to the memory controller.