Programming memory cells with additional data for increased threshold voltage resolution
Methods for data transfer and/or programming a memory device, memory devices and memory systems are provided. According to at least one such method, additional data is appended to original data and the resulting data is programmed in a selected memory cell. The appended data increases the program threshold voltage margin of the original data. The appended data can be a duplicate of the original data or logical zeros. When the selected memory cell is read, the memory control circuitry can read just the original data in the MSB field or the memory control circuitry can read the entire programmed data and ignore the LSB field, for example.
1. A method for data transfer and programming in a memory device, the method comprising:
transferring original data to a memory array;
appending additional digits to the original data to form a new programming word wherein the additional digits comprise mirror bits of the original data; and
programming the new programming word to the memory array.
2. The method of claim 1 wherein transferring the original data comprises a memory control circuitry transferring the original data to the memory array.
3. The method of claim 1 wherein the additional digits comprise a plurality of logical zero bits.
4. The method of claim 1 wherein the original data comprises a plurality of logical bits.
5. The method of claim 1 wherein the original data comprises a logical bit.
6. The method of claim 1 wherein transferring the original data comprises transferring one logical bit and programming the new programming word comprises programming three or more logical bits.
7. The method of claim 1 wherein transferring the original data comprises transferring two logical bits and programming the new programming word comprises programming a plurality of logical bits.
8. The method of claim 1 wherein the additional digits comprise three logical bits.
9. A method for programming a non-volatile memory device, the method comprising:
a memory array receiving, from a control circuit, original data for programming to a selected memory cell;
forming a new data word for programming that comprises the original data as most significant bits and additional data as least significant bits;
programming the new data word to the selected memory cell;
verifying successful programming of the new data word; and
reading the selected memory cell wherein all bits of the new data word are read and the least significant bits are ignored.
10. The method of claim 9 and further including reading the selected memory cell wherein only the most significant bits are read.
11. The method of claim 9 wherein forming the new data word comprises the memory array forming the new data word.
12. The method of claim 9 and further including the control circuit transmitting a plurality of logical bits of original data.
13. The method of claim 9 wherein programming the new data comprises increasing a threshold voltage from an initial erased voltage to a target voltage indicative of the new data word.
14. The method of claim 9 wherein the memory array receiving comprises receiving the original data and the additional data, appended to the original data, from the control circuit.
15. The method of claim 9 wherein the memory array receives n original data bits and appends m bits of the additional data, wherein n is not equal to m.
16. The method of claim 15 wherein the control circuit transmits n+m bits to the memory array.
17. The method of claim 16 wherein n is not equal to m.
18. The method of claim 9 wherein the new data word can open or close a window between data threshold voltage levels in response to the additional data.
19. A non-volatile memory device comprising:
memory control circuitry for controlling operation of the memory device, the memory control circuitry configured to transmit original data; and
a memory array, coupled to the memory control circuitry, that operates in response to the memory control circuitry, the memory array configured to be programmed with the original data and append additional data wherein the appended additional data increases a programmed threshold voltage margin of the original data, wherein the memory control circuitry is further configured to read the programmed original data and appended additional data and ignore the appended additional data.
20. The memory device of claim 19 wherein the memory array comprises a NAND architecture.
21. The memory device of claim 19 wherein the memory control circuitry is configured to read only the original data that was programmed with the appended additional data.
22. A memory system comprising:
a system controller for controlling operation of the memory system with memory signals; and
a memory device, coupled to the control circuit and operating in response to the memory signals, the memory device comprising:
memory control circuitry coupled to the system controller and receiving original data from the system controller; and
an array of memory cells coupled to the memory control circuitry and configured to receive the original data from the memory control circuitry and append additional data to the original data such that the additional data are duplicate of the original data and increases a program threshold voltage margin of the original data.
23. The memory system of claim 22 wherein the array of memory cells is configured to append additional data that are logical zeros.
24. A method for programming a memory device, the method comprising:
forming a new data word from original data for programming a selected memory cell, the new data word comprises a translation of the original data with data that are mirror bits of the original data; and
programming the new data word to the selected memory cell.
25. The method of claim 24 wherein forming the new data word comprises accessing a translation table.
26. The method of claim 24 wherein forming the new data is performed by the memory device.
27. The method of claim 24 wherein a window between threshold voltage levels is either increased or decreased in response to the translation of the original data.
28. The method of claim 27 wherein the window between threshold voltage levels is different between adjacent new data words.
29. The method of claim 25 and further including:
reading data from the selected memory cell;
accessing the translation table to interpret the read data; and
translating the read data back to the original data in response to the translation table.
30. A memory system comprising:
a system controller for controlling operation of the memory system with memory signals; and
a memory device, coupled to the control circuit and operating in response to the memory signals, the memory device comprising:
memory control circuitry coupled to the system controller and receiving original data from the system controller; and
an array of memory cells coupled to the memory control circuitry and configured to receive the original data from the memory control circuitry, append additional data to the original data to form a data combination, and translate the data combination to new data such that the new data are mirror bits of the original data and increases a program threshold voltage margin of the original data.
31. A memory system comprising:
a system controller for controlling operation of the memory system with memory signals wherein the system controller appends additional data to original data to form a data combination, translates the data combination to translated data such that the translated data are mirror bits of the original data and are configured to increase a program threshold voltage margin of the original data in a selected memory cell; and
a memory device, coupled to the system controller and configured to receive the translated data, the memory device comprising:
memory control circuitry coupled to the system controller and receiving the translated data; and
an array of memory cells coupled to the memory control circuitry and configured to store the translated data in a memory cell in response to the memory control circuitry.