IP Library › Granted Patent US 12,346,236
Granted Patent B2
US 12,346,236 · App. 18/248,637 · Granted Jul 1, 2025

Offload server, offload control method, and offload program

Inventor: Yoji Yamato (Musashino, JP)
Assignee: Nippon Telegraph and Telephone Corporation
G06F11/3612G06F11/3698
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Quick Facts
Patent No.
US 12,346,236
App. No.
18/248,637
Granted
Jul 1, 2025
Kind
B2
Abstract

An offload server includes a code analysis section for analyzing whether function blocks executable by an accelerator is included, a processing pattern generation section for generating patterns for offloading the function blocks, and a performance measurement section for deploying each pattern for offloading the function blocks to a verification machine to measure performance. When the performance measured by the performance measurement section satisfies a desired level, the processing pattern generation section generates patterns for offloading remaining loop statements except the function blocks, and the performance measurement section deploys each pattern to a verification environment to measure performance. When the performance measured by the performance measurement section fails to satisfy the desired level, the processing pattern generation section generates patterns for offloading loop statements, and the performance measurement section deploys each pattern to the verification environment to measure performance.

Claims (55)

1. An offload server comprising:

one or more hardware processors;

a code analysis section, implemented using one or more of the one or more hardware processors, configured to analyze whether a source code of a software program includes at least one function block executable by at least one accelerator;

a processing pattern generation section, implemented using one or more of the one or more hardware processors, configured to generate a first plurality of patterns for offloading the at least one function block to the at least one accelerator;

a performance measurement section, implemented using one or more of the one or more hardware processors, configured to deploy each of the first plurality of patterns for offloading the at least one function block to a verification environment to measure a first performance; and

a control section, implemented using one or more of the one or more hardware processors, configured to,

when the first performance measured by the performance measurement section satisfies a desired level, generate a second plurality of patterns for offloading at least one remaining loop statement except the at least one function block in the software program by the processing pattern generation section, and deploy each of the second plurality of patterns to the verification environment to measure a second performance by the performance measurement section, and

when the first performance measured by the performance measurement section fails to satisfy the desired level, generate a third plurality of patterns for offloading at least one loop statement of the software program by the processing pattern generation section, and deploy each of the third plurality of patterns to the verification environment to measure a third performance by the performance measurement section,

wherein the control section is further configured to try the at least one function block and then try the at least one remaining loop statement or the at least one loop statement, as a target to be offloaded to the accelerator, and

wherein the control section is further configured to try a many-core CPU, a GPU, and an FPGA in this order as the accelerator to which the at least one function block, the at least one remaining loop statement, and/or the at least one loop statement is offloaded.

2. An offload server comprising:

one or more hardware processors;

a code analysis section, implemented using one or more of the one or more hardware processors, configured to analyze whether a source code of a software program includes at least one function block executable by at least one accelerator;

a processing pattern generation section, implemented using one or more of the one or more hardware processors, configured to generate a first plurality of patterns for offloading the at least one function block to the at least one accelerator;

a performance measurement section, implemented using one or more of the one or more hardware processors, configured to deploy each of the first plurality of patterns for offloading the at least one function block to a verification environment to measure a first performance; and

a control section, implemented using one or more of the one or more hardware processors, configured to,

when the first performance measured by the performance measurement section satisfies a desired level, generate a second plurality of patterns for offloading at least one remaining loop statement except the at least one function block in the software program by the processing pattern generation section, and deploy each of the second plurality of patterns to the verification environment to measure a second performance by the performance measurement section, and

when the first performance measured by the performance measurement section fails to satisfy the desired level, generate a third plurality of patterns for offloading at least one loop statement of the software program by the processing pattern generation section, and deploy each of the third plurality of patterns to the verification environment to measure a third performance by the performance measurement section,

wherein the at least one accelerator is constituted of a plurality of types of accelerators,

wherein the control section is further configured to select, from each of the first plurality of patterns, the second plurality of patterns, and the third plurality of patterns, a pattern with a highest speed,

wherein the control section is further configured to try the at least one function block and then try the at least one remaining loop statement or the at least one loop statement, as a target to be offloaded to the accelerator, and

wherein the control section is further configured to try a many-core CPU, a GPU, and an FPGA in this order as the accelerator to which the at least one function block, the at least one remaining loop statement, and/or the at least one loop statement is offloaded.

3. An offload server comprising:

one or more hardware processors;

a code analysis section, implemented using one or more of the one or more hardware processors, configured to analyze whether a source code of a software program includes at least one function block executable by at least one accelerator;

a processing pattern generation section, implemented using one or more of the one or more hardware processors, configured to generate a first plurality of patterns for offloading the at least one function block to the at least one accelerator;

a performance measurement section, implemented using one or more of the one or more hardware processors, configured to deploy each of the first plurality of patterns for offloading the at least one function block to a verification environment to measure a first performance; and

a control section, implemented using one or more of the one or more hardware processors, configured to,

when the first performance measured by the performance measurement section satisfies a desired level, generate a second plurality of patterns for offloading at least one remaining loop statement except the at least one function block in the software program by the processing pattern generation section, and deploy each of the second plurality of patterns to the verification environment to measure a second performance by the performance measurement section, and

when the first performance measured by the performance measurement section fails to satisfy the desired level, generate a third plurality of patterns for offloading at least one loop statement of the software program by the processing pattern generation section, and deploy each of the third plurality of patterns to the verification environment to measure a third performance by the performance measurement section,

wherein the at least one accelerator is a plurality of accelerators,

wherein the at least one function block is a plurality of function blocks,

wherein the at least one remaining loop statement for which the second performance is measured or the at least one loop statement for which the third performance is measured is a plurality of performance-measured loop statements, and

wherein the control section is further configured to, regarding offloading of the plurality of function blocks or the plurality of performance-measured loop statements:

when a pattern faster than original processing is found for plural ones of the plurality of accelerators and a same function block or a same loop statement can be offloaded to the plural ones of the plurality of accelerators,

select an accelerator providing higher performance as an offload destination among the plural ones of the plurality of accelerators;

when first different function blocks among the plurality of function blocks or first different loop statements among the plurality of performance-measured loop statements can be offloaded to first different accelerators among the plurality of accelerators and cannot be offloaded to the first different accelerators of a same node,

select an accelerator providing higher performance as an offload destination among the first different accelerators; and

when second different function blocks among the plurality of function blocks or second different loop statements among the plurality of performance-measured loop statements can be offloaded to second different accelerators among the plurality of accelerators and can be offloaded to the second different accelerators of a same node,

select the second different accelerators of the same node as offload destinations of the second different blocks or the second different loop statements.

4. An offload server comprising:

one or more hardware processors;

a code analysis section, implemented using one or more of the one or more hardware processors, configured to analyze whether a source code of a software program includes at least one function block executable by at least one accelerator;

a processing pattern generation section, implemented using one or more of the one or more hardware processors, configured to generate a first plurality of patterns for offloading the at least one function block to the at least one accelerator;

a performance measurement section, implemented using one or more of the one or more hardware processors, configured to deploy each of the first plurality of patterns for offloading the at least one function block to a verification environment to measure a first performance; and

a control section, implemented using one or more of the one or more hardware processors, configured to,

when the first performance measured by the performance measurement section satisfies a desired level, generate a second plurality of patterns for offloading at least one remaining loop statement except the at least one function block in the software program by the processing pattern generation section, and deploy each of the second plurality of patterns to the verification environment to measure a second performance by the performance measurement section, and

when the first performance measured by the performance measurement section fails to satisfy the desired level, generate a third plurality of patterns for offloading at least one loop statement of the software program by the processing pattern generation section, and deploy each of the third plurality of patterns to the verification environment to measure a third performance by the performance measurement section,

wherein the at least one remaining loop statement for which the second performance is measured or the at least one loop statement for which the third performance is measured is at least one performance-measured loop statement, and

wherein the control section is further configured to, regarding offloading of the at least one function block and the at least one performance-measured loop statement:

when an offload destination of the at least one performance-measured loop statement is a node different from an offload destination of the at least one function block,

try a pattern for offloading the at least one function block and not try a pattern for offloading the at least one performance-measured loop statement when a first performance improvement by offloading the at least one performance-measured loop statement is less than or equal to a second performance improvement by offloading the at least one function block, and

try a pattern for offloading the at least one performance-measured loop statement and not try a pattern for offloading the at least one function block when the first performance improvement exceeds the second performance improvement; and

when the offload destination of the at least one performance-measured loop statement is a same node as the offload destination of the at least one function block,

try a pattern for offloading the at least one function block and the at least one performance-measured loop statement.

Assignments (2)
CHANGE OF NAME Recorded Dec 5, 2025
From: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
To: NTT, INC.
Reel/Frame 073861/0410 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2024
From: YAMATO, YOJI
To: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
Reel/Frame 066489/0156 →
Continuity (1)
Related Publication 20230385178A1 · Nov 30, 2023
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Cited By (3)
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