Processing unit performance projection using dynamic hardware behaviors

1. A method comprising:

receiving computer program code to be executed on a first processing unit;

monitoring an execution of the computer program code on the first processing unit to determine a plurality of performance characteristics;

determining a plurality of dynamic hardware behaviors by applying a clustering algorithm to the plurality of performance characteristics, wherein determining a first one of the plurality of dynamic hardware behaviors comprises clustering two or more windows of time during the execution based on corresponding performance characteristics of the first processing unit during the two or more windows of time;

generating a representative set of instructions to collectively represent the two or more windows of time;

generating an equivalent accelerator portion of computer program code by translating the representative set of instructions to an equivalent set of instructions to be executed on a second processing unit, wherein the equivalent set of instructions approximates the representative set of instructions but does not match a functionality of at least one of the two or more windows of time; and

determining, for the first one of the plurality of dynamic hardware behaviors, an estimated measure of performance for executing the equivalent accelerator portion on the second processing unit.

2. The method of claim 1 , wherein monitoring the execution of the computer program code comprises simulating execution of the computer program code on the first processing unit and monitoring the simulated execution.

3. The method of claim 1 , wherein generating the equivalent accelerator portion of computer program code comprises translating the representative set of instructions using a predefined translation database.

4. The method of claim 1 , wherein determining, for the first one of the plurality of dynamic hardware behaviors, the estimated measure of performance comprises simulating execution of the equivalent accelerator portion on the second processing unit.

5. The method of claim 1 , wherein determining the plurality of performance characteristics comprises monitoring a plurality of hardware performance counters of the first processing unit.

6. The method of claim 1 , wherein the estimated measure of performance comprises a time required to execute the equivalent accelerator portion on the second processing unit.

7. The method of claim 1 , wherein the estimated measure of performance comprises a reduction in a time required to execute the equivalent accelerator portion on the second processing unit, as compared to a time required to execute the representative set of instructions on the first processing unit.

8. The method of claim 1 , wherein the estimated measure of performance comprises an efficiency of executing the equivalent accelerator portion on the second processing unit.

9. A computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by one or more computer processors to perform an operation comprising:

receiving machine code configured for a first architecture of a first processing unit;

simulating execution of the machine code on the first processing unit;

monitoring the simulated execution to determine a plurality of performance characteristics;

determining a plurality of dynamic hardware behaviors by applying a clustering algorithm to the plurality of performance characteristics, wherein determining a first one of the plurality of dynamic hardware behaviors comprises clustering two or more windows of time during the execution based on corresponding performance characteristics of the first processing unit during the two or more windows of time;

generating a representative set of instructions to collectively represent the two or more windows of time; and

generating an equivalent accelerator portion of machine code configured for a second architecture of a second processing unit, by translating the representative set of instructions to an equivalent set of instructions configured for the second architecture, wherein the equivalent set of instructions approximates the representative set of instructions but does not match a functionality of at least one of the two or more windows of time.

10. The computer-readable storage medium of claim 9 , the operation further comprising:

determining, for the first one of the plurality of dynamic hardware behaviors, an estimated measure of performance for executing the equivalent accelerator portion on the second processing unit.

11. The computer-readable storage medium of claim 10 , wherein determining, for the first one of the plurality of dynamic hardware behaviors, the estimated measure of performance comprises simulating execution of the equivalent accelerator portion on the second processing unit.

12. The computer-readable storage medium of claim 10 , wherein the estimated measure of performance comprises a time required to execute the equivalent accelerator portion on the second processing unit.

13. The computer-readable storage medium of claim 10 , wherein the estimated measure of performance comprises a reduction in time required to execute the equivalent accelerator portion on the second processing unit, as compared to a time required to execute the representative set of instructions on the first processing unit.

14. The computer-readable storage medium of claim 10 , wherein the estimated measure of performance comprises an efficiency of executing the equivalent accelerator portion on the second processing unit.

15. The computer-readable storage medium of claim 9 , wherein determining the plurality of performance characteristics comprises monitoring a plurality of hardware performance counters of the first processing unit.

16. A system comprising:

a processor; and

a computer memory storing a program, which, when executed on the processor, performs an operation comprising:

receiving computer program code to be executed on a first processing unit;

monitoring an execution of the computer program code on the first processing unit to determine a plurality of performance characteristics;

determining a plurality of dynamic hardware behaviors by applying a clustering algorithm to the plurality of performance characteristics, wherein determining a first one of the plurality of dynamic hardware behaviors comprises clustering two or more windows of time during the execution based on corresponding performance characteristics of the first processing unit during the two or more windows of time;

generating a representative set of instructions to collectively represent the two or more windows of time;

generating an equivalent accelerator portion of computer program code by translating the representative set of instructions to an equivalent set of instructions to be executed on a second processing unit, wherein the equivalent set of instructions approximates the representative set of instructions but does not match a functionality of at least one of the two or more windows of time; and

determining, for the first one of the plurality of dynamic hardware behaviors, an estimated measure of performance for executing the equivalent accelerator portion on the second processing unit.

17. The system of claim 16 , wherein determining, for the first one of the plurality of dynamic hardware behaviors, the estimated measure of performance comprises simulating execution of the equivalent accelerator portion on the second processing unit.

18. The system of claim 16 , wherein the estimated measure of performance comprises a time required to execute the equivalent accelerator portion on the second processing unit.

19. The system of claim 16 , wherein the estimated measure of performance comprises a reduction in a time required to execute the equivalent accelerator portion on the second processing unit, as compared to a time required to execute the representative set of instructions on the first processing unit.

20. The system of claim 16 , wherein the estimated measure of performance comprises an efficiency of executing the equivalent accelerator portion on the second processing unit.