IP Library Granted Patent US 12,376,235
Granted Patent B2
US 12,376,235 · App. 18/258,556 · Granted Jul 29, 2025

Layered plate and wiring base board production method

Inventors: Masaya Toba (Tokyo, JP); Kazuyuki Mitsukura (Tokyo, JP); Masaki Yamaguchi (Tokyo, JP)
H05K1/181H05K3/022H05K2201/0209H05K2201/0358H05K2201/10553H05K2203/1377
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Quick Facts
Patent No.
US 12,376,235
App. No.
18/258,556
Granted
Jul 29, 2025
Kind
B2
Abstract

A layered plate including a copper layer having a thickness of 5 μm or less, and a resin layer provided on a surface of the copper layer, in which a water absorption rate of the resin layer is 1% or less after being left in an environment of 130° C. in temperature and 85% in relative humidity for 200 hours.

Claims (25)

1. A layered plate comprising:

a copper layer having a thickness of 5 μm or less; and

a resin layer provided on a surface of the copper layer,

wherein a water absorption rate of the resin layer is 1% or less after being left in an environment of 130° C. in temperature and 85% in relative humidity for 200 hours.

2. The layered plate according to claim 1 , wherein 90° peel strength of an interface between the copper layer and the resin layer is 0.4 N/mm or more.

3. The layered plate according to claim 1 , wherein 90° peel strength of an interface between the copper layer and the resin layer is 0.25 N/mm or more after being left in an environment of 130° C. in temperature and 85% in relative humidity for 200 hours.

4. The layered plate according to claim 1 , wherein a variation rate of 90° peel strength is-30% to 0% before and after a highly accelerated life test performed in a state in which a sample of the layered plate is left in an environment of 130° C. in temperature and 85% in relative humidity for 200 hours.

5. The layered plate according to claim 1 , further comprising a rust preventive layer between the resin layer and the copper layer.

6. The layered plate according to claim 1 , wherein a relative dielectric constant of the resin layer is 4.5 or less at 10 GHz.

7. The layered plate according to claim 1 , wherein a dielectric loss tangent of the resin layer is 0.05 or less at 10 GHz.

8. The layered plate according to claim 1 , wherein the resin layer contains a thermosetting resin composition.

9. The layered plate according to claim 8 , wherein the resin layer contains a glass cloth impregnated with the thermosetting resin composition.

10. The layered plate according to claim 8 ,

wherein the thermosetting resin composition contains silica filler, and a content of the silica filler is 65% by mass or less based on a total mass of the resin contained in the thermosetting resin composition.

11. A method of manufacturing a circuit board, the method comprising:

preparing a layered plate which includes a copper layer having a thickness of 5 μm or less, a resin layer, and a support substrate in this order, and in which a water absorption rate of the resin layer is 1% or less after being left in an environment of 130° C. in temperature and 85% in relative humidity for 200 hours;

forming a seed layer on a surface of the copper layer by electroless copper plating;

forming a resist pattern including a groove reaching a surface of the seed layer on the surface of the seed layer; and

filling the groove with a conductive material containing copper by electrolysis copper plating.

12. A method of manufacturing a circuit board, the method comprising:

preparing a layered plate which includes a copper layer having a thickness of 5 μm or less, a resin layer, and a support substrate in this order, and in which a water absorption rate of the resin layer is 1% or less after being left in an environment of 130° C. in temperature and 85% in relative humidity for 200 hours;

forming a first opening reaching a surface of the support substrate through the copper layer and the resin layer;

forming a seed layer on a surface of the copper layer and a side surface of the first opening by electroless copper plating;

forming a resist pattern including a second opening communicating with the first opening on a surface of the seed layer; and

filling the first opening and the second opening with a conductive material containing copper by electrolysis copper plating.

Assignments (2)
CHANGE OF ADDRESS Recorded Feb 9, 2024
From: RESONAC CORPORATION
To: RESONAC CORPORATION
Reel/Frame 066547/0677 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2023
From: TOBA, MASAYA; MITSUKURA, KAZUYUKI; YAMAGUCHI, MASAKI
To: RESONAC CORPORATION
Reel/Frame 064396/0816 →