IP Library › Granted Patent US 12,322,335
Granted Patent B2
US 12,322,335 · App. 18/278,552 · Granted Jun 3, 2025

Pixel circuit and driving method therefor, and display panel

Inventors: Changlong Yuan (Beijing, CN); Xilei Cao (Beijing, CN); Li Zhu (Beijing, CN); Benlian Wang (Beijing, CN); Zhenhua Zhang (Beijing, CN)
Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd.; BOE Technology Group Co., Ltd.
G09G3/3233G09G3/3225G09G3/3266G09G3/3275G09G3/3291H10K59/1213G09G2300/0426G09G2300/0452G09G2300/0819G09G2300/0842G09G2300/0852G09G2300/0861G09G2310/0251G09G2310/061G09G2310/08G09G2320/0233G09G2320/0247G09G2320/045G09G2330/021H10K59/1216H10K59/126
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Quick Facts
Patent No.
US 12,322,335
App. No.
18/278,552
Granted
Jun 3, 2025
Kind
B2
Abstract

A pixel circuit and a driving method therefor, and a display panel. The pixel circuit includes a driving circuit, a data writing circuit, a compensation storage circuit, a first light-emitting control circuit and a second light-emitting control circuit. The driving circuit includes a control end, a first end, and a second end, and is configured to control a driving current which flows through the first end and the second end and which is used for driving a light-emitting element to emit light; the data writing circuit is connected to a first scanning signal line and is configured to, in response to a first scanning signal provided by the first scanning signal line, write a data signal into the first end of the driving circuit; the data writing circuit and the first light-emitting control circuit repel one another in a connected state under the control of the first scanning signal.

Claims (43)

1. A pixel circuit, comprising: a driving circuit, a data writing circuit, a compensation storage circuit, a first light-emitting control circuit, and a second light-emitting control circuit,

wherein the driving circuit comprises a control terminal, a first terminal, and a second terminal, and is configured to control a driving current flowing through the first terminal and the second terminal for driving a light-emitting element to emit light;

the data writing circuit is connected to the first terminal of the driving circuit and a first scanning signal line, and is configured to write a data signal to the first terminal of the driving circuit in response to a first scanning signal provided by the first scanning signal line;

the compensation storage circuit is connected to the control terminal and the second terminal of the driving circuit, and is also connected to a second scanning signal line and a first power line, and is configured to store the data signal written by the data writing circuit in response to a second scanning signal provided by the second scanning signal line and to compensate for the driving circuit;

the first light-emitting control circuit is connected to the first terminal of the driving circuit, the first power line, and the first scanning signal line, and is configured to apply a first voltage of the first power line to the first terminal of the driving circuit in response to the first scanning signal provided by the first scanning signal line, wherein a conductive state of the data writing circuit and a conductive state of the first light-emitting control circuit under control of the first scanning signal are mutually exclusive; and

the second light-emitting control circuit is connected to the second terminal of the driving circuit, a light-emitting control signal line, and a first terminal of the light-emitting element, and is configured to apply the driving current to the light-emitting element in response to a light-emitting control signal provided by the light-emitting control signal line,

wherein the first light-emitting control circuit comprises a first light-emitting control transistor, and the data writing circuit comprises a data writing transistor,

a gate electrode of the first light-emitting control transistor comprises a first sub-gate electrode and a second sub-gate electrode located at different layers, and an active layer of the first light-emitting control transistor is located between the first sub-gate electrode and the second sub-gate electrode,

a layer where the first sub-gate electrode is located is between a layer where a gate electrode of the data writing transistor is located and a layer where the second sub-gate electrode is located,

the first sub-gate electrode and the second sub-gate electrode of the first light-emitting control transistor and the gate electrode of the data writing transistor are connected to the first scanning signal line through connection electrodes, respectively, and a layer where the connection electrodes are located is on a side of the layer where the second sub-gate electrode is located away from the layer where the first sub-gate electrode is located and the layer where the gate electrode of the data writing transistor is located.

2. The pixel circuit according to claim 1 , wherein the driving circuit comprises a driving transistor, a gate electrode of the driving transistor serves as the control terminal of the driving circuit, a first electrode of the driving transistor serves as the first terminal of the driving circuit, and a second electrode of the driving transistor serves as the second terminal of the driving circuit.

3. The pixel circuit according to claim 1 , wherein

the gate electrode of the data writing transistor is connected to the first scanning signal line to receive the first scanning signal, a first electrode of the data writing transistor is connected to a data line to receive the data signal, and a second electrode of the data writing transistor is connected to the first terminal of the driving circuit.

4. The pixel circuit according to claim 3 , wherein

the gate electrode of the first light-emitting control transistor is connected to the first scanning signal line to receive the first scanning signal, a first electrode of the first light-emitting control transistor is connected to the first power line to receive the first voltage, and a second electrode of the first light-emitting control transistor is connected to the first terminal of the driving circuit.

5. The pixel circuit according to claim 1 , wherein a type of the data writing transistor is different from a type of the first light-emitting control transistor.

6. The pixel circuit according to claim 1 , wherein the first light-emitting control transistor is an N-type transistor, and the data writing transistor is a P-type transistor.

7. The pixel circuit according to claim 4 , wherein the compensation storage circuit comprises a compensation transistor and a storage capacitor;

a gate electrode of the compensation transistor is connected to the second scanning signal line to receive the second scanning signal, a first electrode of the compensation transistor is connected to the second terminal of the driving circuit, and a second electrode of the compensation transistor is connected to the control terminal of the driving circuit; and

a first electrode of the storage capacitor is connected to the control terminal of the driving circuit, and a second electrode of the storage capacitor is connected to the first power line.

8. The pixel circuit according to claim 1 , wherein the first scanning signal line and the second scanning signal line are same or different, and the first scanning signal and the second scanning signal are same or different.

9. The pixel circuit according to claim 7 , wherein, when the first scanning signal and the second scanning signal are different, a type of the data writing transistor is different from a type of the compensation transistor, and the type of the compensation transistor is the same as a type of the first light-emitting control transistor.

10. The pixel circuit according to claim 1 , further comprising a reset circuit, wherein the reset circuit is connected to an initial voltage terminal, the first terminal of the light-emitting element, and the control terminal of the driving circuit, and is configured to apply a reset voltage provided by the initial voltage terminal to the first terminal of the light-emitting element and the control terminal of the driving circuit in response to a reset signal.

11. The pixel circuit according to claim 10 , wherein the reset circuit comprises a first reset transistor and a second reset transistor;

a gate electrode of the first reset transistor is connected to a first reset signal line to receive a first reset signal as the reset signal, a first electrode of the first reset transistor is connected to the initial voltage terminal to receive the reset voltage, and a second electrode of the first reset transistor is connected to the control terminal of the driving circuit;

a gate electrode of the second reset transistor is connected to a second reset signal line to receive a second reset signal as the reset signal, a first electrode of the second reset transistor is connected to the initial voltage terminal to receive the reset voltage, and a second electrode of the second reset transistor is connected to the first terminal of the light-emitting element.

12. The pixel circuit according to claim 11 , wherein the first reset signal line and the second reset signal line are same or different, and the first reset signal and the second reset signal are same or different.

13. The pixel circuit according to claim 1 , wherein the second light-emitting control circuit comprises a second light-emitting control transistor, a gate electrode of the second light-emitting control transistor is connected to the light-emitting control signal line to receive the light-emitting control signal, a first electrode of the second light-emitting control transistor is connected to the second terminal of the driving circuit, and a second electrode of the second light-emitting control transistor is connected to the first terminal of the light-emitting element.

14. A driving method for the pixel circuit according to claim 1 , comprising a reset phase, a data writing and compensation phase, and a light-emitting phase;

wherein, in the reset phase, a first level of the first scanning signal is input through the first scanning signal line to turn on the first light-emitting control circuit, and the first voltage is applied to the first terminal of the driving circuit through the first light-emitting control circuit that is turned on;

in the data writing and compensation phase, a second level of the first scanning signal is input through the first scanning signal line to turn on the data writing circuit, the second scanning signal is input through the second scanning signal line to turn on the compensation storage circuit, the data signal is input through a data line, the data signal is written into the first terminal of the driving circuit through the data writing circuit that is turned on to turn on the driving circuit, the data signal is stored through the compensation storage circuit that is turned on, and the driving circuit is compensated through the compensation storage circuit that is turned on; and

in the light-emitting phase, the first scanning signal is input through the first scanning signal line to turn on the first light-emitting control circuit and the driving circuit, the light-emitting control signal is input through the light-emitting control signal line to turn on the second light-emitting control circuit, and the driving current is applied to the light-emitting element through the first light-emitting control circuit, the driving circuit, and the second light-emitting control circuit, which are turned on, to cause the light-emitting element to emit light.

15. The driving method according to claim 14 , wherein the pixel circuit further comprises a reset circuit,

wherein the reset circuit is connected to an initial voltage terminal, the first terminal of the light-emitting element, and the control terminal of the driving circuit, and is configured to apply a reset voltage to the first terminal of the light-emitting element and the control terminal of the driving circuit in response to a reset signal,

wherein the method further comprises:

in the reset phase, the reset signal is input to turn on the reset circuit, and the reset voltage is applied to the first terminal of the light-emitting element and the control terminal of the driving circuit through the reset circuit that is turned on.

16. A display panel, comprising the pixel circuit according to claim 1 .

17. The pixel circuit according to claim 2 , wherein

the gate electrode of the data writing transistor is connected to the first scanning signal line to receive the first scanning signal, a first electrode of the data writing transistor is connected to a data line to receive the data signal, and a second electrode of the data writing transistor is connected to the first terminal of the driving circuit.

18. The pixel circuit according to claim 5 , wherein the first light-emitting control transistor is an N-type transistor, and the data writing transistor is a P-type transistor.

19. The pixel circuit according to claim 5 , wherein the compensation storage circuit comprises a compensation transistor and a storage capacitor;

a gate electrode of the compensation transistor is connected to the second scanning signal line to receive the second scanning signal, a first electrode of the compensation transistor is connected to the second terminal of the driving circuit, and a second electrode of the compensation transistor is connected to the control terminal of the driving circuit; and

a first electrode of the storage capacitor is connected to the control terminal of the driving circuit, and a second electrode of the storage capacitor is connected to the first power line.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2023
From: YUAN, CHANGLONG; CAO, XILEI; ZHU, LI; WANG, BENLIAN; ZHANG, ZHENHUA
To: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.; BOE TECHNOLOGY GROUP CO., LTD.
Reel/Frame 064683/0001 →
Priority Claims (2)
WO PCT/CN2021/109890 · Jul 30, 2021 · international
CN 202110898658.9 · Aug 5, 2021 · national
Continuity (2)
Related Publication 20240135875A1 · Apr 25, 2024
Related Publication 20240233637A9 · Jul 11, 2024
References Cited (144)
US 10381426B2 · Ka et al. · 2019 [cited by applicant]
US 10388239B2 · Lin et al. · 2019 [cited by applicant]
US 10431153B2 · Gao et al. · 2019 [cited by applicant]
US 10529283B2 · Chai et al. · 2020 [cited by applicant]
US 10720102B2 · Umeda et al. · 2020 [cited by applicant]
US 10916198B2 · Lin et al. · 2021 [cited by applicant]
US 10984725B1 · He et al. · 2021 [cited by applicant]
US 11049458B1 · Fan et al. · 2021 [cited by applicant]
US 11068092B2 · Han et al. · 2021 [cited by applicant]
US 11222587B2 · Toyomura · 2022 [cited by applicant]
US 11263960B2 · Xiong et al. · 2022 [cited by applicant]
US 11282461B2 · Li et al. · 2022 [cited by applicant]
US 11373582B2 · Lee et al. · 2022 [cited by applicant]
US 11386838B2 · Gao · 2022 [cited by applicant]
US 11393396B2 · Yang et al. · 2022 [cited by applicant]
US 20080150846A1 · Chung · 2008 [cited by applicant]
US 20090028955A1 · Oku · 2009 [cited by applicant]
US 20090289876A1 · Chun · 2009 [cited by applicant]
US 20120105410A1 · Choi et al. · 2012 [cited by applicant]
US 20120147060A1 · Jeong · 2012 [cited by applicant]
US 20150077412A1 · Nakamura · 2015 [cited by applicant]
US 20150154906A1 · Chung · 2015 [cited by applicant]
US 20170124941A1 · Na et al. · 2017 [cited by applicant]
US 20170193901A1 · Wang et al. · 2017 [cited by applicant]
US 20180047337A1 · Zhu et al. · 2018 [cited by applicant]
US 20180301092A1 · Ma · 2018 [cited by applicant]
US 20190005764A1 · Lin et al. · 2019 [cited by applicant]
US 20190005802A1 · Woo et al. · 2019 [cited by applicant]
US 20190057646A1 · Lin et al. · 2019 [cited by applicant]
US 20200160788A1 · Son · 2020 [cited by applicant]
US 20200018489A1 · Dong · 2020 [cited by applicant]
US 20200286972A1 · Seo et al. · 2020 [cited by applicant]
US 20200312223A1 · Yuan et al. · 2020 [cited by applicant]
US 20200388229A1 · Zhang et al. · 2020 [cited by applicant]
US 20200394961A1 · Kim et al. · 2020 [cited by applicant]
US 20210027696A1 · Kim et al. · 2021 [cited by applicant]
US 20210118361A1 · Li · 2021 [cited by applicant]
US 20210125557A1 · Na · 2021 [cited by applicant]
US 20210174736A1 · Yang et al. · 2021 [cited by applicant]
US 20210193049A1 · Lin et al. · 2021 [cited by applicant]
US 20210225282A1 · Cho et al. · 2021 [cited by applicant]
US 20210280130A1 · Wang et al. · 2021 [cited by applicant]
US 20210287605A1 · Wang et al. · 2021 [cited by applicant]
US 20210366397A1 · Na · 2021 [cited by applicant]
US 20210375193A1 · Son et al. · 2021 [cited by applicant]
US 20210383752A1 · Yang · 2021 [cited by examiner]
US 20210407383A1 · Lai et al. · 2021 [cited by applicant]
US 20220005414A1 · Liu et al. · 2022 [cited by applicant]
US 20220130322A1 · Yuan et al. · 2022 [cited by applicant]
US 20220013996A1 · Li et al. · 2022 [cited by applicant]
US 20220016521A1 · Huang et al. · 2022 [cited by applicant]
US 20220157238A1 · Wang et al. · 2022 [cited by applicant]
US 20220165984A1 · Choi et al. · 2022 [cited by applicant]
US 20220208932A1 · Yun · 2022 [cited by applicant]
US 20220270552A1 · Roh et al. · 2022 [cited by applicant]
US 20220310017A1 · Yang · 2022 [cited by applicant]
US 20220343852A1 · Wang et al. · 2022 [cited by applicant]
US 20220376024A1 · Zheng et al. · 2022 [cited by applicant]
US 20230036060A1 · Wang et al. · 2023 [cited by applicant]
US 20240000137A1 · Zhang et al. · 2024 [cited by applicant]
US 20240013727A1 · Zhang et al. · 2024 [cited by applicant]
CN 102467876A · 2012 [cited by applicant]
CN 103778889A · 2014 [cited by applicant]
CN 102568374B · 2015 [cited by applicant]
CN 105427803A · 2016 [cited by applicant]
CN 105427806A · 2016 [cited by applicant]
CN 205920745U · 2017 [cited by applicant]
CN 106910468A · 2017 [cited by applicant]
CN 107146577A · 2017 [cited by applicant]
CN 107256695A · 2017 [cited by applicant]
CN 107274830A · 2017 [cited by applicant]
CN 107358918A · 2017 [cited by applicant]
CN 107564468A · 2018 [cited by applicant]
CN 107610651A · 2018 [cited by applicant]
CN 108133687A · 2018 [cited by applicant]
CN 108206008A · 2018 [cited by applicant]
CN 108777130A · 2018 [cited by applicant]
CN 109215582A · 2019 [cited by applicant]
CN 109215585A · 2019 [cited by applicant]
CN 109285500A · 2019 [cited by applicant]
CN 109427293A · 2019 [cited by applicant]
CN 109509427A · 2019 [cited by applicant]
CN 109599062A · 2019 [cited by applicant]
CN 109817165A · 2019 [cited by applicant]
CN 110021273A · 2019 [cited by applicant]
CN 110033734A · 2019 [cited by applicant]
CN 110176213A · 2019 [cited by applicant]
CN 110648629A · 2020 [cited by applicant]
CN 110660360A · 2020 [cited by applicant]
CN 110767163A · 2020 [cited by applicant]
CN 111158514A · 2020 [cited by applicant]
CN 111199711A · 2020 [cited by applicant]
CN 111354307A · 2020 [cited by applicant]
CN 111354314A · 2020 [cited by applicant]
CN 111435587A · 2020 [cited by applicant]
CN 111445854A · 2020 [cited by applicant]
CN 111489700A · 2020 [cited by applicant]
CN 111508426A · 2020 [cited by applicant]
CN 111583866A · 2020 [cited by applicant]
CN 111710299A · 2020 [cited by applicant]
CN 111724745A · 2020 [cited by applicant]
CN 111754922A · 2020 [cited by applicant]
CN 111754938A · 2020 [cited by applicant]
CN 111883055A · 2020 [cited by applicant]
CN 112053661A · 2020 [cited by applicant]
CN 112086062A · 2020 [cited by applicant]
CN 112116890A · 2020 [cited by applicant]
CN 112133253A · 2020 [cited by applicant]
CN 112309316A · 2021 [cited by applicant]
CN 112331678A · 2021 [cited by applicant]
CN 112382235A · 2021 [cited by applicant]
CN 112397026A · 2021 [cited by applicant]
CN 112397029A · 2021 [cited by applicant]
CN 112397030A · 2021 [cited by applicant]
CN 112397565A · 2021 [cited by applicant]
CN 112420794A · 2021 [cited by applicant]
CN 112435630A · 2021 [cited by applicant]
CN 112599099A · 2021 [cited by applicant]
CN 112712774A · 2021 [cited by applicant]
CN 112753065A · 2021 [cited by applicant]
CN 112767873A · 2021 [cited by applicant]
CN 112992071A · 2021 [cited by applicant]
CN 113097247A · 2021 [cited by applicant]
CN 113140179A · 2021 [cited by applicant]
CN 113224123A · 2021 [cited by applicant]
CN 113450717A · 2021 [cited by applicant]
CN 113838419A · 2021 [cited by applicant]
CN 114627807A · 2022 [cited by applicant]
CN 114694586A · 2022 [cited by applicant]
JP 2007011214A · 2007 [cited by applicant]
JP 2019128447A · 2019 [cited by applicant]
KR 20090122119A · 2009 [cited by applicant]
KR 20130007214A · 2013 [cited by applicant]
KR 20130055450A · 2013 [cited by applicant]
KR 20170049778A · 2017 [cited by applicant]
WO WO2019037543A1 · 2019 [cited by examiner]
WO 2019163402A1 · 2019 [cited by applicant]
WO 2020037767A1 · 2020 [cited by applicant]
Mar. 1, 2024—(US) Non-Final Office Action—U.S. Appl. No. 18/273,695. [cited by applicant]
Jun. 13, 2024—(US) Non-Final Office Action—U.S. Appl. No. 17/788,727. [cited by applicant]
Jun. 25, 2024—(US) Non-Final Office Action—U.S. Appl. No. 18/279,621. [cited by applicant]
Aug. 12, 2024—(US) Non-Final Office Action—U.S. Appl. No. 18/270,094. [cited by applicant]
Dec. 13, 2024—(CN) First Office Action—App 2021108973199 with English translation. [cited by applicant]
Nov. 22, 2024—(CN) First Office Action—App 2021108986837 with English translation. [cited by applicant]