IP Library › Granted Patent US 12,610,707
Granted Patent B2
US 12,610,707 · App. 18/284,622 · Granted Apr 21, 2026

Display apparatus, electronic device, and method of manufacturing semiconductor device

Inventors: Minato Ito (Atsugi, JP); Munehiro Kozuma (Atsugi, JP); Yuki Okamoto (Atsugi, JP); Yusuke Koumura (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H10K59/1315H10K59/1201H10K59/1213H10K59/127
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Quick Facts
Patent No.
US 12,610,707
App. No.
18/284,622
Granted
Apr 21, 2026
Kind
B2
Abstract

A display apparatus with a driver circuit having redundancy is provided. The display apparatus includes a first layer and a second layer positioned above the first layer. The first layer includes a first driver circuit and a second driver circuit. The second layer includes a first pixel region and a second pixel region. The first pixel region includes a first pixel circuit and the second pixel region includes a second pixel circuit. The first pixel region includes a region overlapping with the first circuit and the second pixel region includes a region overlapping with the second circuit. The first pixel circuit is electrically connected to the first driver circuit through a first wiring, the second pixel circuit is electrically connected to the second driver circuit through a second wiring, and the first wiring is electrically connected to the second wiring through a switch.

Claims (40)

1 . A display apparatus comprising:

a first layer; and

a second layer over the first layer,

wherein the first layer comprises a first driver circuit and a second driver circuit,

wherein the second layer comprises a first pixel region and a second pixel region,

wherein the first pixel region comprises a first pixel circuit,

wherein the second pixel region comprises a second pixel circuit,

wherein the first pixel region comprises a region overlapping with the first driver circuit,

wherein the second pixel region comprises a region overlapping with the second driver circuit,

wherein the first pixel circuit is electrically connected to the first driver circuit through a first wiring,

wherein the second pixel circuit is electrically connected to the second driver circuit through a second wiring,

wherein the first wiring is electrically connected to the second wiring through a switch,

wherein when the switch is off, the first driver circuit is configured to transmit first image data to the first pixel circuit and the second driver circuit is configured to transmit second image data to the second pixel circuit, and

wherein when the switch is on, the first driver circuit is configured to transmit the first image data to the first pixel circuit and to transmit the second image data to the second pixel circuit.

2 . The display apparatus according to claim 1 ,

wherein the switch is included in the first layer or the second layer.

3 . The display apparatus according to claim 1 ,

wherein the first layer comprises a first substrate,

wherein the second layer comprises a second substrate,

wherein each of the first substrate and the second substrate is a semiconductor substrate containing silicon as a material,

wherein a channel formation region of each transistor included in the first driver circuit and the second driver circuit contains silicon included in the first substrate, and

wherein a channel formation region of each transistor included in the first pixel region and the second pixel region contains silicon included in the second substrate.

4 . The display apparatus according to claim 1 ,

wherein the first layer comprises a first substrate,

wherein the first substrate is a semiconductor substrate containing silicon as a material,

wherein each transistor included in the first driver circuit and the second driver circuit is a transistor formed over the first substrate, and

wherein each transistor included in the first pixel region and the second pixel region is a transistor containing a metal oxide in a channel formation region.

5 . An electronic device comprising:

the display apparatus according to claim 1 ; and

a housing.

6 . A method of manufacturing a semiconductor device comprising a second substrate,

wherein the second substrate is a semiconductor substrate containing silicon as a material,

wherein the method comprises a first step to a seventh step,

wherein the first step comprises a step of forming a separation layer over the second substrate,

wherein the second step comprises a step of forming a well in a region of the second substrate other than a region where the separation layer is formed,

wherein the third step comprises a step of forming a first insulator over a part of a region of the second substrate where the well is formed,

wherein the fourth step comprises a step of forming a first low-resistance region and a second low-resistance region in a region of the second substrate other than regions where the separation layer and the first insulator are formed,

wherein the fifth step comprises a step of transferring the process to the sixth step in the case where a malfunction occurs in one of a first driver circuit and a second driver circuit included in a first substrate, and transferring the process to the seventh step in the case where a malfunction occurs in neither the first driver circuit nor the second driver circuit included in the first substrate,

wherein the sixth step comprises a step of removing the first insulator and a step of forming a third low-resistance region in a region of the second substrate where the first insulator is formed, and

wherein the seventh step comprises a step of forming a second insulator over the second substrate, a step of providing an opening in a region of the second insulator overlapping with the separation layer, the first low-resistance region, and the second low-resistance region, and a step of forming a conductor in the opening.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2023
From: ITO, MINATO; KOZUMA, MUNEHIRO; OKAMOTO, YUKI; KOUMURA, YUSUKE
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 065060/0441 →
Priority Claims (1)
JP 2021-060330 · Mar 31, 2021 · national
Continuity (1)
Related Publication 20240179987A1 · May 30, 2024
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