Sigma-delta modulator based analog-to-digital converter and dithering method thereof
View Patent ↗The disclosed invention is a sigma-delta modulator based ADC and a dithering method thereof. An analog dither circuit of an input stage in a quantizer, which is configured to perform dithering, receives an integrator output signal from an output of an integrator and a plurality of digital dither signals from digital dither generator, and employs these signals to produce multi-level analog dither signals via the operation of a plurality of transistors as switches coupled with a plurality of resistors coupled in series. The multi-level analog dither signals can prevent, reduce, or eliminate limit cycle in the sigma-delta modulator based ADC. Furthermore, disclosed invention does not require fixed load capacitance, resulting in no extra power consumption and solve the problem as the kickback noise variation.
1. A sigma-delta modulator based analog-to-digital converter (ADC) ( 100 ), comprising:
a digital dither generator ( 101 ) configured to provide a plurality of digital dither signals S di the digital dither generator ( 101 ) comprising a dither pattern generator ( 601 ) and a binary decoder ( 602 );
a sigma-delta modulator loop ( 102 ) configured to receive an input analog signal S in and the plurality of digital dither signals S di , and to provide a quantizer output signal S q ; and
a processor ( 103 ) configured to provide a digital representation of the input analog signal S in ;
where the sigma-delta modulator loop ( 102 ) comprising
an integrator ( 104 ) configured to provide an integrator output signal S int ;
a feedback digital to analog converter (DAC) ( 105 ) configured to receive the quantizer output signal S q and to produce a feedback signal S fb ; and
a quantizer ( 106 ) configured to receive the integrator output signal S int and the plurality of digital dither signals S di and to output the quantizer output signal S q ,
where the quantizer ( 106 ) comprising
an input stage ( 201 ) configured to receive the integrator output signal S int and the plurality of digital dither signals S di and to provide an output signal S cmp ; and
a gain stage ( 202 ) configured to receive the output signal S cmp and to output the quantizer output signal S q ;
where the input stage ( 201 ) comprising
a current source ( 301 );
a pair of input transistors ( 302 ) configured to produce first and second output current signals S curr_a , S curr_b in relation to the integrator output signal S int and a threshold signal S threshold ;
a load network ( 303 ) configured to convert the first and second output current signals S curr_a , S curr_b into the output signals S cmp_a , S cmp_b of the input stage ( 201 ); and
an analog dither circuit ( 304 )
characterized in that
the analog dither circuit ( 304 ), coupled in series between the current source ( 301 ) and the pair of input transistors ( 302 ) and configured to receive the plurality of digital dither signals S di and to divide a bias current from the current source ( 301 ) to each transistor of the pair of input transistors ( 302 ).
2. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 1 wherein the analog dither circuit ( 304 ) comprises
a plurality of resistors ( 401 ) coupled in series and configured to provide resistance; and
a plurality of transistors as switches ( 402 ) configured to function as switches.
3. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein the plurality of resistors ( 401 ) provide resistance between a first source terminal S source_a of the pair of input transistors ( 302 ) to an output S current of the current source ( 301 ) and a second source terminal S source_b of the pair of input transistors ( 302 ) to the output S current of the current source ( 301 ).
4. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 or 3 wherein the plurality of resistors ( 401 ) providing resistance depending on current division ratio of the divided current.
5. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein the transistors of the plurality of transistors as switches ( 402 ) are coupled with terminals of resistors of the plurality of resistors ( 401 ) at drain terminals.
6. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein the plurality of transistors as switches ( 402 ) are coupled with the plurality of digital dither signals S di at control terminals ( 405 ).
7. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein the plurality of transistors as switches ( 402 ) are coupled with the output S current of the current source ( 301 ) at source terminals ( 406 ).
8. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein each transistor of the plurality of transistors as switches ( 402 ) is configured to provide a current path from the output S current of the current source ( 301 ) to one of the terminals of the plurality of resistors ( 401 ) when one of the transistors of the plurality of transistors as switches ( 402 ) is turned on.
9. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 or 8 wherein the transistor of the plurality of transistors as switches ( 402 ) providing the current path is controlled by the plurality of digital dither signals S di .
10. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 or 8 wherein each transistor of the plurality of transistors as switches ( 402 ) is configured to receive each signal of the plurality of digital dither signals S di .
11. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein left and right terminals of the plurality of resistors ( 403 , 404 ) are coupled to the first and second source terminals S source_a , S source_b respectively of the pair of input transistors ( 302 ).
12. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein a number of the plurality of transistors as switches ( 402 ) are the same as a number of the plurality of digital dither signals S di ; and
a number of the plurality of resistors ( 401 ) are at least one more than the number of the plurality of transistors as switches ( 402 ).
13. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein the plurality of resistors ( 401 ) can be replaced by a plurality of transistors, configured to function as resistors, biased in linear region.
14. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein all resistors in the plurality of resistors ( 401 ) can be of the same predetermined values.
15. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 2 wherein each transistor of the plurality of transistors as switches ( 402 ) is only coupled with one digital dither signal from the plurality of digital dither signals S di .
16. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 1 wherein the plurality of digital dither signals S di is generated from the binary decoder ( 602 ) and then received by the analog dither circuit ( 304 ).
17. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 16 wherein the binary decoder ( 602 ) is N-to-M binary decoder ( 701 ) configured to decode a plurality of binary representation of a dither pattern S di_bin and produce the plurality of digital dither signal S di ,
wherein a number of decoded output bits (M) are correlated to a number of a binary coded input (N), calculated as M=2.
18. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 1 wherein the analog dither circuit ( 304 ), coupled in series between the first and second source terminals S source_a , S source_b of the pair of input transistors ( 302 ) and to the output S current of the current source ( 301 ).
19. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 1 wherein the current division ratio of the divided current depends on the plurality of digital dither signals S di .
20. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 1 or 19 wherein the plurality of digital dither signals S di control the current division ratio by controlling which transistor belonging to the plurality of transistors as switches ( 402 ) to turn on.
21. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 1 or 19 wherein the current division ratio from the first and second source terminals S source_a , S source_b of the pair of input transistors ( 302 ) affects the first and second output current signals S curr_a , S curr_b .
22. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 1 wherein the first and second output current signals S curr_a , S curr_b affects, in proportional values, the first and second output signals S cmp_a , S cmp_b of the input stage ( 201 ).
23. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 1 wherein only one digital dither signal from the plurality of digital dither signals S di can be of logic HIGH at a given time.
24. The sigma-delta modulator based analog-to-digital converter (ADC) of claim 1 or 23 wherein only one digital dither signal from the plurality of digital dither signals S di to be logic HIGH can control a transistor in the plurality of transistors as switches ( 402 ) to turn on.
25. A dithering method of sigma-delta based modulator analog-to-digital converter (ADC), comprising:
receiving an input analog signal S in and a feedback signal Se at an integrator ( 104 ) to provide an integrator output signal S int ;
receiving the integrator output signal S int and a plurality of digital dither signal S di at an input stage ( 201 ) of a quantizer ( 106 ) and comparing the integrator output signal S int and the plurality of digital dither signal S di against a threshold signal S threshold to produce an output signal S cmp of the input stage ( 201 );
amplifying the output signal S cmp of the input stage ( 201 ) at a gain stage ( 202 ) to produce a quantizer output signal S q ;
receiving the quantizer output signal S q at a processor ( 103 ) to produce a plurality of output digital signals S out as a digital representation of the input analog signal S in ;
characterized in that
receiving the plurality of digital dither signals S di at control terminals ( 405 ) of a plurality of transistors as switches ( 402 ) to control the plurality of transistors as switches ( 402 ) as turning on or off;
providing current from a current source ( 301 ) to first and second source terminals S source_a , S source_b of a pair of input transistors ( 302 ) through the plurality of transistors as switches ( 402 ) and a plurality of resistors ( 401 ) respectively;
receiving the integrator output signal S int and the threshold signal S threshold at control terminals ( 305 ) of the pair of input transistors ( 302 );
producing first and second output current signals S curr_a , S curr_b in relation to the integrator output signal S int and the threshold signal S threshold ; and
converting the first and second output current signals S curr_a , S curr_b at a load network ( 303 ) to the output signals S cmp_a , S cmp_b of the input stage ( 201 ).
26. The dithering method of sigma-delta based modulator analog-to-digital converter (ADC) of claim 25 , further comprising generating the plurality of digital dither signals S di at a binary decoder ( 602 ) of a digital dither generator ( 101 ).
27. The dithering method of sigma-delta based modulator analog-to-digital converter (ADC) of claim 26 wherein
generating the plurality of digital dither signals S di includes generating logic HIGH and LOW of the plurality of digital dither signals S di ; and
propagating the logic HIGH and LOW of the plurality of digital dither signals S di wherein controlling the plurality of transistors as switches ( 402 ) to turn on or off.
28. The dithering method of sigma-delta based modulator analog-to-digital converter (ADC) of claim 27 wherein controlling the plurality of transistors as switches ( 402 ) to turn on if logic HIGH and controlling the plurality of transistors as switches ( 402 ) to turn off if logic LOW.
29. The dithering method of sigma-delta based modulator analog-to-digital converter (ADC) of claim 25 , further comprising providing current path by one of transistors of the plurality of transistors as switches ( 402 ) turned on, from an output S current of the current source ( 301 ) to one of terminals of the plurality of resistors ( 401 ).
30. The dithering method of sigma-delta based modulator analog-to-digital converter (ADC) of claim 25 , further comprising dividing current between the first and second source terminals S source_a , S source_b of the pair of input transistors ( 302 ) according to the current division ratio of the divided current wherein controlled by transistor of the plurality of transistors as switches ( 402 ) which is turned on.