IP Library › Granted Patent US 12,277,070
Granted Patent B2
US 12,277,070 · App. 18/295,866 · Granted Apr 15, 2025

Cache line subscription

Inventors: Eric Ola Harald Liljedahl (Stockholm, SE); Jatin Bhartia (Cambridge, GB)
Assignee: Arm Limited
G06F12/12G06F12/0891
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Quick Facts
Patent No.
US 12,277,070
App. No.
18/295,866
Granted
Apr 15, 2025
Kind
B2
Abstract

An apparatus with an additional storage element or field is provided where a subscription indicator is stored, indicating a subscription to a region of memory, and hence subscribing to a cache line corresponding to the region of memory. In response to a subscribed cache line being invalidated, the apparatus performs actions to re-fetch the cache line, and to store the cache line in the cache after a short delay. The subscription indicator may be stored in a variety of ways, and may include further information that influences the functionality of the present techniques. Such further information may be adjustable in order to dynamically control the functionality of the disclosed techniques for a particular implementation over time.

Claims (63)

1. An apparatus comprising:

subscription storage circuitry configured to store a subscription indicator indicating a subscription to a region of memory;

control circuitry configured to generate, in response to an invalidation in a cache of a cache line holding a data block corresponding to the region of memory for which the subscription is indicated, a re-fetch request specifying the data block after a delay, and to cause the data block to be stored in the cache; and

decoding circuitry configured to decode a subscription instruction indicating the region of memory, wherein

in response to the subscription instruction, the decoding circuitry is configured to generate control signals which cause the subscription indicator to be stored in the subscription storage circuitry.

2. An apparatus comprising:

subscription storage circuitry configured to store a subscription indicator indicating a subscription to a region of memory;

control circuitry configured to generate, in response to an invalidation in a cache of a cache line holding a data block corresponding to the region of memory for which the subscription is indicated, a re-fetch request specifying the data block after a delay, and to cause the data block to be stored in the cache; and

subscription determination circuitry configured to store the subscription indicator in the subscription storage circuitry in response to at least one of:

receiving a snoop request indicating an intent to modify the data block; and

a number of times that the data block has been allocated to the cache exceeding a threshold within a monitoring period.

3. The apparatus of claim 1 , wherein

the control circuitry is responsive to storage of the subscription indicator in the subscription storage circuitry, to determine whether the data block is currently stored in the cache, and

in response to a determination that the data block is not currently validly stored in the cache, the control circuitry is configured to generate a fetch request specifying the data block.

4. The apparatus of claim 1 , wherein

the subscription indicator comprises an indication of the region of memory, and the subscription storage circuitry comprises a storage element separate from the cache.

5. The apparatus of claim 4 , wherein

the control circuitry is configured to cancel the subscription indicator in response to storage of a new subscription indicator in the storage element, when

the storage element has insufficient storage capacity to store the new subscription indicator in addition to the subscription indicator.

6. The apparatus of claim 1 , wherein

the subscription indicator is stored in a field of the cache line holding the data block corresponding to the region of memory.

7. The apparatus of claim 6 , wherein

the field of the cache line is configured to store a flag.

8. The apparatus of claim 1 , wherein

the subscription indicator comprises a delay value; and

the delay is based on the delay value.

9. The apparatus of claim 8 , wherein

the control circuitry is configured to adjust the delay value in response to at least one of:

a further invalidation of the cache line within a re-invalidation time of the invalidation; and

a determination of whether the cache received a memory access request specifying the cache line within the re-invalidation time.

10. The apparatus of claim 8 , wherein

the control circuitry is configured to adjust the delay value based on whether the data block is indicated as being read-only or having shared ownership with another processing element or indicated as having been modified by another processing element.

11. The apparatus of claim 1 , wherein

the subscription indicator comprises a confidence value, wherein

in response to the confidence value being below a confidence threshold, the control circuitry is configured to treat the subscription as not indicated.

12. The apparatus of claim 11 , wherein

the control circuitry is configured to increase the confidence value in response to at least one of:

the data block being stored in the cache in response to a data processing instruction; and

receiving a snoop request specifying the cache line while the cache line is stored in the cache and the subscription indicator is stored in the subscription storage circuitry.

13. The apparatus of claim 11 , wherein

the control circuitry is configured to decrease the confidence value in response to at least one of:

an exception; and

expiry of a subscription ageing period.

14. The apparatus of claim 1 , wherein

the control circuitry is configured to move the subscription indicator to further storage circuitry; and

in response to a subsequent re-subscription to the region of memory, the control circuitry is configured to cause the subscription indicator to be moved from the further storage circuitry to the subscription storage circuitry.

15. The apparatus of claim 1 , wherein

the control circuitry is configured to cancel the subscription indicator in response to the cache line holding the data block corresponding to the region of memory being evicted from the cache.

16. The apparatus of claim 15 , wherein

the cache is configured to prioritise evicting a different cache line over the cache line holding the data block corresponding to the region of memory.

17. The apparatus of any of claim 1 , wherein

the cache is coupled to a processing element; and

the invalidation of the cache line is in response to an invalidation request from a further processing element; and

the control circuitry is configured to cause the re-fetch request to be sent as a snoop request to the further processing element.

18. A data processing system comprising:

the apparatus of claim 1 ;

a further system component configured to generate an invalidation request, and to send the invalidation request to the apparatus;

the apparatus is configured to cause the invalidation of the cache line holding the data block in response to the invalidation request; and

the control circuitry is configured to cause the re-fetch request to be sent to the further system component.

19. A method comprising:

storing, in subscription storage circuitry, a subscription indicator indicating a subscription to a region of memory;

generating, in response to an invalidation in a cache of a cache line holding a data block corresponding to the region of memory for which the subscription is indicated, a re-fetch request specifying the data block after a delay, and causing the data block to be stored in the cache; and

in response to a subscription instruction indicating the region of memory, generating control signals which cause the subscription indicator to be stored in the subscription storage circuitry.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 5, 2023
From: LILJEDAHL, ERIC OLA HARALD; BHARTIA, JATIN
To: ARM LIMITED
Reel/Frame 063225/0575 →
Continuity (1)
Related Publication 20240338323A1 · Oct 10, 2024
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