Fault diagnostics
View Patent ↗Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.
1 . A method comprising:
receiving a layout of a circuit comprising a plurality of cells, the layout comprising placement information of a first cell and a second cell of the circuit;
determining a cell orientation for each of the first cell and the second cell;
determining a base orientation for each of the first cell and the second cell from the cell orientation;
determining, from the base orientation, a bridge pair comprising a first boundary node of the first cell facing a second boundary node of the second cell;
modeling of the bridge pair as another circuit; and
generating a test pattern for the modeled bridge pair.
2 . The method of claim 1 , wherein the test pattern comprises automatic test pattern generation (ATPG) pattern.
3 . The method of claim 1 , wherein generating the test pattern comprises generating an input pattern and an expected output for the input pattern for the bridge pair.
4 . The method of claim 1 , wherein modeling the bridge pair between the bridge pair comprises modelling the bridge pair fault between an internal node to internal node bridge pair.
5 . The method of claim 1 , wherein modeling the bridge pair comprises modelling a bridge pair fault between an internal node to an external node bridge pair.
6 . The method of claim 1 , wherein the second cell abuts the first cell and is separated from the first cell by a boundary circuit.
7 . The method of claim 1 , further comprising determining a fault coverage of the circuit from the generated test pattern.
8 . The method of claim 7 , further comprising inserting, in response to determining that the fault coverage is less than a predetermined level, a filler cell between the first cell and the second cell.
9 . The method of claim 8 , further comprising determining the bridge pair for the circuit with the inserted filler cell.
10 . An apparatus comprising:
a memory storage; and
a processing unit coupled to the memory storage, wherein the processing unit is operative to:
receive a circuit layout comprising placement information of the plurality of cells of the circuit;
identify, from the placement information, a first cell abutting a second cell from the circuit layout, the second cell being separated from the first cell by a boundary circuit;
identify a bridge pair between the first cell and the second cell, the bridge pair comprising a first boundary node of the first cell paired with a second boundary node of the second cell;
model the bridge pair as another circuit comprising a resistive element connected to a predetermined potential; and
generate a test pattern for the modeled bridge pair.
11 . The apparatus of claim 1 , wherein the processing unit is further operative to determine a fault coverage of the circuit layout from the generated pattern.
12 . The apparatus of claim 11 , wherein the processing unit is further operative to insert, in response to determining that the fault coverage is less than a predetermined level, a filler cell between the first cell and the second cell.
13 . The apparatus of claim 12 , wherein the processing unit is further operative to determine the bridge pair for the circuit layout with the inserted filler cell.
14 . The apparatus of claim 10 , wherein the bridge pair comprises an internal node to internal node bridge pairs.
15 . A non-transitory computer-readable medium that stores a set of instructions which when executed perform a method comprising:
receiving a layout of a circuit comprising a plurality of cells, the layout comprising placement information of the plurality of cells of the circuit;
identifying a bridge pair in the circuit from the layout, wherein identifying the bridge pair comprises:
identifying a first cell abutting a second cell from the layout, the second cell being separated from the first cell by a boundary circuit, and
identifying the bridge pair between the first cell and the second cell, the bridge pair comprising a first boundary node of the first cell paired with a second boundary node of the second cell;
determining whether to model the bridge pair as another circuit; and
generating a test pattern for the bridge pair.
16 . The non-transitory computer-readable medium of claim 15 , further comprising:
modeling the bridge pair as the another circuit comprising a resistive element connected to a predetermined potential.
17 . The non-transitory computer-readable medium of claim 15 , further comprising determining a fault coverage of the circuit from the test pattern.
18 . The non-transitory computer-readable medium of claim 17 , further comprising inserting, in response to determining that the fault coverage is less than a predetermined level, a filler cell between the first cell and the second cell.
19 . The non-transitory computer-readable medium of claim 18 , further comprising determining the bridge pair for the circuit with the inserted filler cell.
20 . The non-transitory computer-readable medium of claim 15 , wherein the bridge pair comprises an internal node to internal node bridge pair.