Integrated circuit and method for forming the same
An integrated circuit includes a strip structure having a front side and a back side. The integrated circuit includes a gate structure on the front side of the strip structure. The integrated circuit includes an isolation structure surrounding the strip structure. The integrated circuit includes a backside via in the isolation structure. The integrated circuit includes a contact over the strip structure, wherein a first portion of the contact extends into the isolation structure and contacts the backside via. The integrated circuit includes a backside power rail on the back side of the strip structure and in contact with the backside via.
1. An integrated circuit, comprising:
a strip structure having a front side and a back side, wherein the strip structure comprises a dielectric material;
a gate structure on the front side of the strip structure, wherein a bottommost surface of the gate structure is below a topmost surface of the strip structure;
an isolation structure surrounding the strip structure;
a backside via in the isolation structure;
a contact over the strip structure, wherein a first portion of the contact extends into the isolation structure and contacts the backside via; and
a backside power rail on the back side of the strip structure and in contact with the backside via.
2. The integrated circuit of claim 1 , wherein the strip structure comprises a plurality of dielectric layers.
3. The integrated circuit of claim 1 , wherein the gate structure comprises a gate all around (GAA) structure.
4. The integrated circuit of claim 1 , wherein the bottommost surface of the gate structure is below the topmost surface of the strip structure.
5. The integrated circuit of claim 1 , further comprising an epitaxial structure over the strip structure.
6. The integrated circuit of claim 5 , wherein the contact is electrically connected to the epitaxial structure.
7. The integrated circuit of claim 5 , wherein the contact physically contacts multiple sidewalls of the epitaxial structure.
8. The integrated circuit of claim 1 , further comprising:
a second contact on the front side of the strip structure; and
an epitaxial structure on the first side of the strip structure, wherein the second contact is electrically connected to the epitaxial structure.
9. The integrated circuit of claim 8 , further comprising a dielectric layer, wherein the epitaxial structure directly contacts the dielectric layer.
10. The integrated circuit of claim 9 , wherein the epitaxial structure is between the second contact and the dielectric layer in a direction parallel to a top surface of the strip structure.
11. An integrated circuit, comprising:
a first strip structure;
an isolation structure adjacent to the first strip structure;
a backside via in the isolation structure;
a first epitaxy structure over the first strip structure; and
a first contact over the first epitaxy structure, wherein a first portion of the first contact extends along an entirety of an outermost sidewall, in a direction parallel to a top surface of the isolation structure, of the first epitaxy structure.
12. The integrated circuit of claim 11 , further comprising a second strip structure, wherein the backside via is between the first strip structure and the second strip structure.
13. The integrated circuit of claim 12 , further comprising:
a second epitaxy structure over the second strip structure; and
a second contact over the second epitaxy structure, wherein the second contact extends along a sidewall of the second epitaxy structure.
14. The integrated circuit of claim 13 , wherein the first contact electrically connects to the backside via, and the second contact is electrically separated from the backside via.
15. The integrated circuit of claim 13 , further comprising a dummy fin between the first epitaxy structure and the second epitaxy structure.
16. The integrated circuit of claim 11 , wherein a bottommost surface of the first contact structure is below a bottommost surface of the first epitaxy structure.
17. A method, comprising:
patterning a substrate to define a semiconductor strip over the substrate;
forming a backside via adjacent to the semiconductor strip;
depositing a dielectric material over a conductive material and a dielectric liner;
etching the dielectric material and the dielectric liner to define an isolation structure having a top surface lower than a top surface of the semiconductor strip;
forming a source/drain structure over the semiconductor strip;
forming an interlayer dielectric layer over the source/drain structure;
etching the interlayer dielectric layer and the isolation structure to define an opening exposing the backside via; and
forming a source/drain contact in the opening.
18. The method of claim 17 , wherein etching the interlayer dielectric layer comprises defining the opening extending through the isolation structure.
19. The method of claim 17 , wherein forming the source/drain structure comprises epitaxially growing the source/drain structure.
20. The method of claim 17 , further comprising:
removing the semiconductor strip to define a strip opening; and
depositing a dielectric material into the strip opening.