Architecture to prevent controller-to-controller deadlock
An integrated circuit chip includes a secondary controller coupled to a deadlock solver that provides a communication interface to a primary controller. The deadlock solver stores control logic executable to detect a reset event indicator on a secondary controller that is indicative of a reset event pattern executing on the secondary controller while the secondary controller is in a reset state. Based at least in part on detection of the reset event indicator, the deadlock solver transmits a signal pattern to the secondary controller that mimics a transaction from a primary controller. The signal pattern assisting the secondary controller in exiting a reset state.
1 . An integrated circuit (IC) comprising:
a deadlock solver that provides a communication interface between a primary controller and a secondary controller, the deadlock solver storing control logic executable to:
detect a reset event indicator on the secondary controller, the reset event indicator being indicative of a reset event pattern executing on the secondary controller while the secondary controller is in a reset state; and
based at least in part on detection of the reset event indicator, transmit a signal pattern to the secondary controller that mimics a transaction from a primary controller, the transaction including a clock signal that the secondary controller uses to reset an internal clock during a reset pattern that the secondary controller performs to exit the reset state.
2 . The IC of claim 1 , further comprising:
first switching circuitry configured to selectably toggle a data input source of an SDA signal provided to the secondary controller, the data input source being selectably toggled between an on-chip data source and an off-chip data source;
second switching circuitry configured to selectably toggle a clock input source of a serial clock (SCL) signal provided to the secondary controller, the clock input source being selectably toggled between an on-chip clock and an off-chip clock.
3 . The IC of claim 2 , wherein control logic of the deadlock solver is further executable to:
drive the on-chip clock and the on-chip data source to transmit the signal pattern that mimics the transaction from the primary controller while the on-chip data source is selected as the data input source of the SDA signal and while the on-chip clock is selected as the clock input source of the SCL signal.
4 . The IC of claim 2 , wherein the control logic of the deadlock solver is further executable to:
after transmitting the signal pattern, select the off-chip data source as the data input source of the SDA signal to the secondary controller;
monitor external signals emitted by at the off-chip clock and the off-chip data source; and
based at least in part on detecting a start signature of a predefined event type in the external signals, select the off-chip clock as the clock input source of the SCL signal to the secondary controller.
5 . The IC of claim 1 , wherein the primary controller and the secondary controller are configured to communicate through the deadlock solver via an I3C protocol.
6 . The IC of claim 4 , wherein the predefined event type includes a start condition.
7 . The IC of claim 4 , wherein the predefined event type includes detection of a posedge in a signal generated by the off-chip clock.
8 . The IC of claim 2 , wherein the secondary controller is configured to:
based at least in part on exiting the reset state, monitor signals emitted by the off-chip clock and the off-chip data source; and
based at least in part on determining that the signals satisfy a Bus Idle Condition, pull the SDA signal to a zero state and wait for the primary controller to assign a dynamic address to the secondary controller.
9 . A method comprising:
detecting a reset event indicator on a secondary controller, the reset event indicator being indicative of a reset event pattern executing on the secondary controller while the secondary controller is in a reset state; and
based at least in part on detection of the reset event indicator, transmitting a signal pattern to the secondary controller that mimics a transaction from a primary controller, the transaction including a clock signal that the secondary controller uses to reset an internal clock during a reset pattern that the secondary controller performs to exit the reset state.
10 . The method of claim 9 , wherein the signal pattern is transmitted to the secondary controller from a deadlock solver, the deadlock solver providing a communication interface between the secondary controller and a primary controller.
11 . The method of claim 10 , wherein the deadlock solver further includes:
first switching circuitry configured to selectably toggle a data input source of an SDA signal received at the secondary controller, the data input source being selectably toggled between an on-chip data source and an off-chip data source; and
second switching circuitry configured to selectably toggle a clock input source of a serial clock (SCL) signal received at the secondary controller, the clock input source being selectably toggled between an on-chip clock and an off-chip clock.
12 . The method of claim 11 , wherein transmitting the signal pattern further comprises:
driving the on-chip clock and the on-chip data source to transmit the signal pattern while the on-chip data source is selected as the data input source of the SDA signal and while the on-chip clock is selected as the data input source of the SCL signal.
13 . The method of claim 11 , further comprising:
after transmitting the signal pattern, selecting the off-chip data source as the data input source of the SDA signal to the secondary controller;
monitoring external signals emitted by the off-chip clock and the off-chip data source; and
based at least in part on detecting a start signature of a predefined event type in the external signals, selecting the off-chip clock as the clock input source of the SCL signal to the secondary controller.
14 . The method of claim 9 , wherein the primary controller and the secondary controller are configured to communicate via an I3C protocol.
15 . The method of claim 13 , wherein detecting the start signature of the predefined event type includes detecting a start condition or detecting a posedge in the SCL signal.
16 . The method of claim 13 , further comprising:
monitoring, by the secondary controller, the SDA signal and the SCL signal;
based at least in part on determining that the SDA signal and the SCL signal satisfy a Bus Idle Condition, pulling the SDA signal to a zero state and waiting for a primary controller to assign a dynamic address to the secondary controller.
17 . A system comprising:
first switching circuitry configured to selectably toggle a data input source of an SDA signal input to a secondary controller, the data input source being selectably toggled between an on-chip data source and an off-chip data source;
second switching circuitry configured to selectably toggle a clock input source of a serial clock (SCL) signal to the secondary controller, the clock input source being selectably toggled between an on-chip clock and an off-chip clock; and
control logic executable to detect a reset event indicator on the secondary controller and, based at least in part on the detection of the reset event indicator:
drive the on-chip clock and the on-chip data source to transmit a signal pattern while the on-chip data source is selected as the data input source of the SDA signal and while the on-chip clock is selected as the clock input source of the SCL signal, the signal pattern mimicking a transaction from a primary controller that is effective to assist the secondary controller in exiting a reset state.
18 . The system of claim 17 , wherein the control logic is further executable to:
after transmitting the signal pattern, select the off-chip data source as the data input source of the SDA signal to the secondary controller;
monitor external signals emitted by at the off-chip clock and the off-chip data source; and
based at least in part on detection of a start signature of a predefined event type in the external signals, select the off-chip clock as the clock input source of the SCL signal to the secondary controller.
19 . The system of claim 17 , wherein the primary controller and the secondary controller are configured to communicate via an I3C protocol.
20 . The system of claim 18 , wherein detection of the predefined event type includes detection of a start condition or detection of a posedge in the SCL signal.