Semiconductor device for programming or erasing select transistors and method of operating the same
In a semiconductor memory device, a program voltage is applied to select lines, which are coupled to corresponding select transistors included in a plurality of string groups. A verify operation on the select transistors is then performed, which simultaneously checks the operation of first select transistors included in a first string group and second select transistors included in a second string group.
1 . A method of operating a semiconductor device, comprising:
applying a program voltage to select lines, which are coupled to corresponding select transistors that is included in at least one string group of a plurality of string groups; and
performing a verify operation on the select transistors,
wherein performing the verify operation comprises:
performing a verify check operation on first select transistors that is included in a first string group, of the plurality of string groups; and applying a verify voltage to a select line coupled to second select transistors that is included in a second string group of the plurality of string groups,
wherein the performing the verify check operation on the first select transistors and the applying the verify voltage to a select line coupled to the second select transistors are performed simultaneously.
2 . The method according to claim 1 , wherein performing the verify operation comprises:
applying the verify voltage to a first select line coupled to the first select transistors; and
performing the verify check operation on the first select transistors and applying the verify voltage to a second select line coupled to the second select transistors.
3 . The method according to claim 2 , wherein performing the verify operation further comprises:
performing a verify check operation on the second select transistors and applying the verify voltage to a third select line coupled to third select transistors included in a third string group, of the plurality of string groups.
4 . The method according to claim 3 , wherein performing the verify operation further comprises:
performing a verify check operation on the third select transistors and applying the verify voltage to a fourth select line coupled to fourth select transistors included in a fourth string group, of the plurality of string groups.
5 . The method according to claim 1 , wherein the select transistors comprise a drain select transistor.
6 . The method according to claim 1 , wherein the select transistors comprise a source select transistor.
7 . The method according to claim 1 , wherein performing the verify operation comprises:
applying the verify voltage to a first select line coupled to the first select transistors and then storing results of verification of the first select transistors in first latch circuits comprising corresponding page buffers;
storing values, stored in the first latch circuits, in corresponding second latch circuits, respectively;
storing results of verification of the second select transistors in the first latch circuits, respectively; and
performing a verify check operation on the first select transistors based on values stored in the second latch circuits,
wherein storing the results of verification of the second select transistors in the first latch circuits, respectively, and performing the verify check operation on the first select transistors based on the values stored in the second latch circuits are simultaneously performed.
8 . The method according to claim 7 , wherein the results of verification of the first select transistors are logic values indicating whether respective threshold voltages of the first select transistors are greater than the verify voltage.
9 . The method according to claim 7 , wherein performing the verify check operation on the first select transistors comprises:
determining, based on the values stored in the second latch circuits, whether a number of transistors having threshold voltages greater than the verify voltage, of the first select transistors, is greater than a preset reference value.
10 . The method according to claim 7 , further comprising:
storing values, stored in the first latch circuits, in corresponding second latch circuits, respectively;
storing results of verification of third select transistors included in a third string group, of the plurality of string groups, in the first latch circuits, respectively; and
performing a verify check operation on the second select transistors based on values stored in the second latch circuits,
wherein storing results of verification of the third select transistors in the first latch circuits, respectively, and performing the verify check operation on the second select transistors are simultaneously performed.
11 . The method according to claim 10 , further comprising:
storing values, stored in the first latch circuits, in corresponding second latch circuits, respectively;
storing results of verification of fourth select transistors included in a fourth string group, of the plurality of string groups, in the first latch circuits, respectively; and
performing a verify check operation on the third select transistors based on values stored in the second latch circuits,
wherein storing the results of verification of the fourth select transistors in the first latch circuits, respectively, and performing the verify check operation on the third select transistors are simultaneously performed.
12 . A method of operating a semiconductor device, comprising:
applying a program voltage to select lines, which are coupled to corresponding select transistors included in first to N-th string groups; and
performing a verify operation on the select transistors,
wherein performing the verify operation comprises:
performing a verify check operation on i-th select transistors included in an i-th string group, of the first to N-th string groups; and
applying a verify voltage to a select line coupled to (i+1)-th select transistors included in an (i+1)-th string group,
wherein the performing the verify check operation on the i-th select transistors and the applying the verify voltage to the select line coupled to the (i+1)-th select transistors are performed simultaneously, where N is a natural number equal to or greater than 2, and i is a natural number equal to or greater than 1 and less than N.
13 . The method according to claim 12 , wherein performing the verify operation on the select transistors comprises:
applying the verify voltage to an i-th select line coupled to the i-th select transistors and then storing results of verification of the i-th select transistors in first latch circuits in corresponding page buffers;
storing values, stored in the first latch circuits, in corresponding second latch circuits, respectively;
storing results of verification of the (i+1)-th select transistors in the first latch circuits respectively; and
performing a verify check operation on the i-th select transistors based on values stored in the second latch circuits,
wherein storing the results of verification of the (i+1)-th select transistors in the first latch circuits, respectively, and performing the verify check operation on the i-th select transistors based on the values stored in the second latch circuits are simultaneously performed.
14 . A semiconductor device, comprising:
a first string group comprising first select transistors;
a second string group comprising second select transistors;
a peripheral circuit comprising a plurality of page buffers, each of the plurality of page buffers comprising a first latch circuit and a second latch circuit and which is configured to perform a program operation on the first and second select transistors; and
a control logic configured to control the program operation of the peripheral circuit,
wherein the control logic is configured to control the peripheral circuit to:
apply a verify voltage to the first select transistors and then store results of verification of the first select transistors in first latch circuits of corresponding page buffers, respectively,
store values, stored in the first latch circuits, in corresponding second latch circuits, respectively, and
simultaneously perform an operation of storing the results of verification of the second select transistors in the first latch circuits, respectively, and a verify check operation on the first select transistors based on the values stored in the second latch circuits.
15 . The semiconductor device according to claim 14 , wherein the first and second select transistors comprise at least one drain select transistor.
16 . The semiconductor device according to claim 14 , wherein the first and second select transistors comprise at least one source select transistor.
17 . The semiconductor device according to claim 14 , wherein the peripheral circuit comprises a pass-fail check circuit, which is coupled to the second latch circuits.
18 . The semiconductor device according to claim 17 , wherein the pass-fail check circuit is configured to determine, based on values stored in the second latch circuits, whether a number of select transistors having threshold voltages higher than the verify voltage, of the first select transistors, is greater than a preset reference value.
19 . A method of operating a semiconductor device, comprising:
applying an erase voltage to select transistors included in first to N-th string groups; and
performing a verify operation on the select transistors,
wherein performing the verify operation comprises:
performing a verify check operation on i-th select transistors included in an i-th string group, of the first to N-th string groups; and
applying a verify voltage to a select line coupled to (i+1)-th select transistors included in an (i+1)-th string group,
wherein the performing the verify check operation on the i-th select transistors and the applying the verify voltage to the select line coupled to the (i+1)-th select transistors are performed simultaneously, where N is a natural number equal to or greater than 2, and i is a natural number equal to or greater than 1 and less than N.
20 . The method according to claim 19 , wherein performing the verify operation on the select transistors comprises:
applying the verify voltage to an i-th select line coupled to the i-th select transistors and then storing results of verification of the i-th select transistors in first latch circuits in corresponding page buffers;
storing values, stored in the first latch circuits, in corresponding second latch circuits, respectively;
storing results of verification of the (i+1)-th select transistors in the first latch circuits respectively; and
performing a verify check operation on the i-th select transistors based on values stored in the second latch circuits,
wherein storing the results of verification of the (i+1)-th select transistors in the first latch circuits, respectively, and performing the verify check operation on the i-th select transistors based on the values stored in the second latch circuits are simultaneously performed.