Granted Patent B2

US 11,049,579 · App. 16/849,875 · Granted Jun 29, 2021

Inventor: Fu-Chang Hsu (San Jose, CA)

G11C16/3459G11C16/12G11C16/24G11C16/30

Abstract

Claims (48)

1. A method for programming a NAND flash memory, wherein the NAND flash memory comprises strings of memory cells that are coupled to bit lines and word lines, the method comprising:

programming selected memory cells by applying a program voltage to selected bit lines and an inhibit voltage to unselected bit lines;

verifying the operation of programming by:

precharging the selected bit lines with a bias voltage level while the unselected bit lines maintain the inhibit voltage;

applying a verify voltage to a selected word line that is coupled to the selected memory cells;

discharging the selected bit lines that are coupled to on-cells over a first time interval;

sensing a sensed voltage level on a selected bit line;

loading the selected bit line with the inhibit voltage level when the sensed voltage level is above a threshold level and the program voltage when the sensed voltage level is equal to or below the threshold level; and

repeating the operations of sensing and loading for each of the selected bit lines;

reprogramming a portion of the selected memory cells that are coupled to bit lines loaded with the program voltage; and

repeating the operations of verifying and reprogramming until all the selected memory cells are programmed.

2. The method of claim 1 , wherein the program voltage is 0 volts and the inhibit voltage is one of VDD or VDD−Vt.

3. The method of claim 1 , wherein the bias voltage level is in the range of Vt to VDD.

4. The method of claim 1 , wherein the first time interval is in the range of 1 microsecond to 30 microseconds.

5. The method of claim 1 , wherein the operation of precharging comprises:

enabling select gates that selectively enable and disable the bit lines;

applying the bias voltage to the selected bit lines; and

disabling the select gates to store the bias voltage using the bit line capacitances of the selected bit lines, respectively.

6. The method of claim 1 , wherein the operation of sensing comprises:

enabling a select gate associated with the selected bit line; and

coupling the selected bit line to a sensing device to determine the sensed voltage.

7. The method of claim 1 , wherein the operation of loading comprises:

enabling a select gate associate with the selected bit line;

loading the selected bit line with the inhibit voltage level when the sensed voltage level is above the threshold level and the program voltage when the sensed voltage level is equal to or below the threshold level; and

disabling the select gate associate with the selected bit line to store the loaded voltage using bit line capacitance.

8. A method for operating a NAND flash memory, the method comprising:

precharging selected bit lines of selected memory cells with a bias voltage level while unselected bit lines maintain the inhibit voltage;

applying a verify voltage to a selected word line that is coupled to the selected memory cells;

discharging the selected bit lines that are coupled to on-cells over a first time interval;

sensing a sensed voltage level on a selected bit line;

loading the selected bit line with the inhibit voltage level when the sensed voltage level is above a threshold level and a program voltage when the sensed voltage level is equal to or below the threshold level; and

repeating the operations of sensing and loading for each of the selected bit lines.

9. The method of claim 8 , further comprising programming the selected memory cells before the operation of precharging.

10. The method of claim 8 , further comprising reprogramming a portion of the selected memory cells that are coupled to bit lines loaded with the program voltage after the operations of sensing and loading are complete.

11. A method for reading a multiple level cell NAND flash memory, wherein the NAND flash memory comprises strings of memory cells that are coupled to bit lines and word lines and a single bit data latch coupled to the bit lines, the method comprising:

reading a bit of the cell by performing operations of:

applying a selected word line voltage level to the cell to sense an output of the cell;

flipping the latch to a first data value when the output indicates that the cell is an off-cell; and

repeating the operations of applying and flipping until all word line voltages have been applied to the cell so that the value of the bit is stored in the latch; and

repeating the operation of reading for each bit of the cell to be read.

12. The method of claim 11 , further comprising initializing the latch to a second data value before the operation of applying.

13. The method of claim 12 , wherein the first data value is 0 volts and the second data value is VDD.

14. The method of claim 12 , wherein the first data value is VDD and the second data value is 0 volts.

15. The method of claim 12 , wherein the operation of flipping further comprises leaving the latch unchanged when the output indicates that the cell is an on-cell.

16. The method of claim 12 , wherein the single bit data latch is implemented using complementary logic and wherein the operation of flipping comprises flipping the latch to the first data value when the output indicates that the cell is an on-cell.

17. The method of claim 16 , wherein the first data value is 0 volts and the second data value is VDD.

18. The method of claim 16 , wherein the first data value is VDD and the second data value is 0 volts.

19. The method of claim 16 , wherein the operation of flipping further comprises leaving the latch unchanged when the output indicates that the cell is an off-cell.

Assignments (1)

Continuity (11)

Cited By (3)

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