Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle

1. An apparatus comprising:

a duty cycle adjuster (DCA) configured to adjust a duty cycle of a clock signal; and

a mode register configured to store a DCA code in a plurality of opcodes, wherein the duty cycle is adjusted through the DCA code, wherein the mode register is further configured to store a separate second DCA code in the plurality of opcodes, wherein the DCA code is for an upper byte and the second DCA code for a lower byte.

2. The apparatus of claim 1 , wherein a first four of the plurality of opcodes store the DCA code and a second four of the plurality of opcodes store the second DCA code.

3. The apparatus of claim 1 , wherein the DCA code and the second DCA code each comprises four bits.

4. The apparatus of claim 3 , wherein four of the plurality of opcodes each store one bit of the DCA code and another four of the plurality of opcodes each store one bit of the second DCA code.

5. The apparatus of claim 1 , wherein the clock signal comprises an internal data clock signal.

6. The apparatus of claim 1 , further comprising a clock divider, wherein the DCA is located before the clock divider.

7. A memory device comprising:

an input clock buffer configured to receive a data clock signal and provide an internal data clock signal; and

a duty cycle adjuster (DCA) configured to receive the data clock signal from the input clock buffer and adjust a duty cycle of the data clock signal within a DCA range, based at least in part, on a DCA code, wherein a first plurality of DCA codes cause the DCA to increase the duty cycle of the data clock signal and a second plurality of DCA codes cause the DCA to decrease the duty cycle of the data clock signal.

8. The memory device of claim 7 , wherein the DCA range is divided into a plurality of steps.

9. The memory device of claim 8 , wherein a difference between a first step and a second step is different than a difference between the second step and a third step.

10. The memory device of claim 8 , wherein the plurality of steps are nonlinear.

11. The memory device of claim 8 , wherein the plurality of steps comprises a step range between step 0 to step 7(−7).

12. The memory device of claim 7 , wherein at least one DCA code causes the DCA to maintain the duty cycle of the data clock signal.

13. A memory device comprising:

an input clock buffer configured to receive a data clock signal and provide an internal data clock signal; and

a duty cycle adjuster (DCA) configured to receive the data clock signal from the input clock buffer and adjust a duty cycle of the data clock signal within a DCA range, based at least in part, on a DCA code, wherein the DCA affects the duty cycle of the data clock signal for one or more of read, read32, write, write32, masked write, mode register read, read first-in-first-out (FIFO), write FIFO, read DQ calibration, and duty cycle monitor operations.

14. A method comprising:

receiving, at a memory a mode register write command and a duty cycle adjuster (DCA) code;

responsive to the mode register write command, storing the DCA code in a mode register of the memory; and

based, at least in part, on the DCA code, adjusting a duty cycle of an internal data clock signal with a DCA.

15. The method of claim 14 , wherein adjusting the duty cycle comprises increasing the duty cycle.

16. The method of claim 14 , wherein adjusting the duty cycle comprises decreasing the duty cycle.

17. The method of claim 14 , wherein the DCA code is one of a plurality of DCA codes and indicates a step size by which to adjust the duty cycle, wherein at least two of the DCA codes of the plurality of DCA codes have different step sizes.

18. The method of claim 17 , wherein the step sizes are non-linear.

19. The method of claim 14 , wherein the DCA code comprises a first DCA code for a first byte and a second DCA code for a second byte.