Separation method and assembly for chip-on-wafer processing
A method for separating semiconductor die stacks of a chip-on-wafer assembly is disclosed herein. In one example, divider walls are arranged in a pattern on a first surface of a device wafer such that regions between the divider walls define mounting sites. Die stacks are mounted to the device wafer, wherein individual die stacks are located at a corresponding mounting site between the divider walls. The device wafer is cut through from a second surface that is opposite the first surface of the device wafer, and the divider walls are removed from between the die stacks to form a vacant lane between adjacent die stacks.
1 . A chip-on-wafer (COW) assembly, comprising:
a device wafer having a first surface and a second surface that is opposite from the first surface, wherein the device wafer includes separations extending from the first surface to the second surface;
die stacks mounted to the first surface of the device wafer in a pattern, wherein individual die stacks are located at a corresponding mounting site, wherein each of the die stacks comprises at least one semiconductor die;
divider walls forming intersecting lines of the pattern between the die stacks at the first surface of the device wafer, the divider walls comprising divider wall material that is a water-soluble material or a solvent dissolvable material, wherein each of the divider walls is at least partially vertically aligned with a respective one of the separations; and
a molding material formed over and encasing the die stacks at the first surface of the device wafer.
2 . The COW assembly of claim 1 wherein the die stacks have sides facing the divider walls, and wherein at least one side of at least one of the die stacks forms an integral interface with the divider wall material.
3 . The COW assembly of claim 1 wherein the divider wall material is pre-formed into the intersecting lines of the pattern prior to being adhered to the first surface of the device wafer.
4 . The COW assembly of claim 1 wherein the divider wall material is dispensed between the die stacks after the die stacks are mounted to the first surface.
5 . The COW assembly of claim 1 wherein the device wafer further includes separations extending from the second surface to the first surface and vertically aligned with the divider walls.
6 . The COW assembly of claim 5 wherein the separations split the device wafer having individual portions each corresponding to one of the individual die stacks.
7 . The COW assembly of claim 1 wherein the die stacks include an inner surface mounted to the first surface of the device wafer and an outer surface opposite the inner surface, and wherein the COW assembly further comprises a carrier film formed over the outer surface.
8 . A semiconductor assembly, comprising:
a device wafer having a first surface and a second surface that is opposite from the first surface, wherein the device wafer includes a plurality of trenches arranged in a first grid array, each of the plurality of trenches extending from the second surface to the first surface;
divider walls arranged in a second grid array vertically offset from the first surface of the device wafer, the second grid array defining a plurality of mounting regions in openings in the second grid array, wherein the divider walls comprise a water-soluble divider wall material or a solvent dissolvable divider wall material;
a plurality of die stacks coupled to the first surface of the device wafer, wherein each individual die stack of the plurality of die stacks is positioned in one of the plurality of mounting regions in the second grid array; and
a molding compound formed around the divider walls and each of the plurality of die stacks.
9 . The semiconductor assembly of claim 8 wherein the divider walls are aligned with dicing lanes in the device wafer.
10 . The semiconductor assembly of claim 9 wherein the device wafer further includes separations extending from the second surface to the first surface in each of the dicing lanes.
11 . The semiconductor assembly of claim 9 wherein each of the dicing lanes has a first width, and wherein each of the divider walls has a second width less than the first width.
12 . The semiconductor assembly of claim 9 wherein each of the dicing lanes has a first width, wherein each of the divider walls has a second width equal to the first width, and wherein each of the divider walls has side surfaces in contact with individual die stacks positioned in adjacent mounting regions in the second grid array.
13 . The semiconductor assembly of claim 8 wherein each individual die stack of the plurality of die stacks includes a top surface, and wherein the semiconductor assembly further comprises a carrier film attached to the top surface of each die stack.
14 . The semiconductor assembly of claim 8 wherein the divider walls have a first height, and wherein each individual die stack of the plurality of die stacks has a second height equal to the first height.