Semiconductor device with enhanced avalanche ruggedness
A method includes: receiving the semiconductor device, wherein the semiconductor device includes: a well region; a doped region; a plurality of gate electrodes; a plurality of source regions; and a plurality of drain regions, wherein the plurality of gate electrodes, the plurality of source region and the plurality of drain regions form a plurality of transistors; and a bulk region disposed in the doped region. A first distance measured between a first transistor of the plurality of transistors and the bulk region is greater than a second distance measured between a second transistor of the plurality of transistors and the bulk region. The method further includes: applying a first voltage to the plurality of drain regions, wherein a first avalanche current generated around the first transistor and shunted through the bulk region is greater than a second avalanche current generated around the second transistor and shunted through the bulk region.
1 . A method of operating a semiconductor device, comprising:
receiving the semiconductor device, the semiconductor device comprising:
a well region in a substrate;
a doped region in the substrate over the well region;
a plurality of gate electrodes disposed over the doped region and electrically coupled to each other;
a plurality of source regions in the substrate and electrically coupled together;
a plurality of drain regions in the substrate and electrically coupled together, wherein the plurality of gate electrodes, the plurality of source regions and the plurality of drain regions form a plurality of transistors, respectively; and
a bulk region disposed in the doped region at a periphery of the doped region,
wherein a first distance measured between a first transistor of the plurality of transistors and the bulk region is greater than a second distance measured between a second transistor of the plurality of transistors and the bulk region; and
applying a first voltage to the plurality of drain regions, wherein a first avalanche current generated around the first transistor and shunted through the first transistor is generated earlier than a second avalanche current generated around the second transistor and shunted through the second transistor.
2 . The method of claim 1 , wherein the well region includes a ring shape from a top-view perspective.
3 . The method of claim 1 , wherein the well region includes an N-type dopant.
4 . The method of claim 1 , further comprising stopping application of the first voltage to the plurality of drain regions, wherein a first leakage current of the semiconductor device free of application of the first voltage is substantially equal to a second leakage current of the semiconductor device before application of the first voltage.
5 . The method of claim 1 , wherein a first parasitic bipolar junction transistor (BJT) is formed of the doped region, a first drain region of the drain regions and a first source region of the source regions, wherein the first BJT is turned on to shunt the first avalanche current in response to the first voltage.
6 . The method of claim 5 , wherein a second parasitic BJT is formed of the doped region, a second drain region of the drain regions and a second source region of the source regions, wherein a first base resistance measured between the first parasitic BJT and ground is greater than a second base resistance measured between the second parasitic BJT and ground.
7 . The method of claim 6 , wherein the second parasitic BJT is turned off in response to the first voltage.
8 . The method of claim 6 , wherein the semiconductor device further comprises a resistor electrically coupling the bulk region to ground.
9 . The method of claim 8 , wherein the resistor is disposed in the substrate.
10 . The method of claim 8 , wherein the resistor is formed as a well-type resistor arranged in a second well region in the substrate.
11 . The method of claim 1 , wherein the well region laterally surrounds the plurality of transistors.
12 . The method of claim 1 , wherein the doped region is contiguous across the plurality of transistors.
13 . A method of operating a semiconductor device, comprising:
receiving the semiconductor device, the semiconductor device comprising:
a well region in a substrate;
a doped region in the substrate over the well region;
a plurality of gate electrodes disposed over the doped region and electrically coupled to each other;
a plurality of source regions in the substrate and electrically coupled together;
a plurality of drain regions in the substrate and electrically coupled together, wherein the plurality of gate electrodes, the plurality of source regions and the plurality of drain regions form a plurality of transistors, respectively; and
a bulk region disposed in the doped region at a periphery of the doped region,
wherein a first distance measured between a first transistor of the plurality of transistors and the bulk region is greater than a second distance measured between a second transistor of the plurality of transistors and the bulk region;
measuring a first leakage current of the semiconductor device;
applying a first voltage to the plurality of drain regions to cause a first avalanche current to occur in a first parasitic bipolar junction transistor corresponding to the first transistor earlier than a second parasitic bipolar junction transistor corresponding to the second transistor; and
stopping application of the first voltage to the plurality of drain regions and measuring a second leakage current of the semiconductor device, wherein the second leakage current is substantially equal to the first leakage current.
14 . The method of claim 13 , wherein the applying of the first voltage to the plurality of drain regions causes a second avalanche current to occur around the second transistor, wherein the first avalanche current occurs earlier than the second avalanche current.
15 . The method of claim 13 , wherein the bulk region has an N-type dopant.
16 . The method of claim 13 , wherein the well region extends below the doped region.
17 . A semiconductor device, comprising:
a well region in a substrate;
a doped region in the substrate over the well region;
a plurality of gate electrodes disposed over the doped region and electrically coupled to each other;
a plurality of source regions in the substrate and electrically coupled together;
a plurality of drain regions in the substrate and electrically coupled together, wherein the plurality of gate electrodes, the plurality of source regions and the plurality of drain regions form a plurality of transistors, respectively; and
a bulk region disposed in the doped region at a periphery of the doped region,
wherein a first distance measured between a first transistor of the plurality of transistors and the bulk region is greater than a second distance measured between a second transistor of the plurality of transistors and the bulk region,
wherein when the semiconductor device is configured to receive a first voltage at the plurality of drain regions to generate an avalanche current, a first avalanche current generated around the first transistor and shunted through the first transistor is generated earlier than a second avalanche current generated around the second transistor and shunted through the second transistor.
18 . The semiconductor device of claim 17 , wherein the doped region is surrounded by the well region from a lateral side and a lower side of the doped region.
19 . The semiconductor device of claim 17 , further comprising a first resistor formed in the substrate and electrically coupling the bulk region to ground.
20 . The semiconductor device of claim 17 , further comprising a first parasitic bipolar junction transistor (BJT) formed of the doped region, a drain region of the first transistor and a source region of the first transistor.