Method for forming semiconductor structure
A method for forming a semiconductor structure is provided. The method includes forming a first active region, forming an interlayer dielectric layer over a source/drain region of the first active region, forming a gate stack to surround the channel region of the first active region, and etching the gate stack and the interlayer dielectric layer to form a cutting trench. The cutting trench includes a first portion extending into the gate stack and a second portion extending into the interlayer dielectric layer. A first width of the first portion of the cutting trench is different than a second width of the second portion of the cutting trench in a direction parallel to a longitudinal axis of the gate stack. The method also includes forming a gate cutting structure in the cutting trench.
1 . A method for forming a semiconductor structure, comprising:
forming a first active region;
forming an interlayer dielectric layer over a source/drain region of the first active region;
forming a gate stack to surround the channel region of the first active region;
etching the gate stack and the interlayer dielectric layer to form a cutting trench, wherein the cutting trench includes a first portion extending into the gate stack and a second portion extending into the interlayer dielectric layer, and a first width of the first portion of the cutting trench is different than a second width of the second portion of the cutting trench in a direction parallel to a longitudinal axis of the gate stack; and
forming a gate cutting structure in the cutting trench.
2 . The method for forming the semiconductor structure as claimed in claim 1 , wherein the gate stack is cut into two segments which are electrically isolated from each other by the gate cutting structure.
3 . The method for forming the semiconductor structure as claimed in claim 1 , wherein the first width is wider than the second width.
4 . The method for forming the semiconductor structure as claimed in claim 1 , wherein the first active region includes a lower fin element, and the channel region of the first active region includes a plurality of nanostructures vertically stacked over the lower fin element.
5 . The method for forming the semiconductor structure as claimed in claim 4 , further comprising:
forming an isolation structure adjacent to the lower fin element of the first active region, wherein the gate stack and the interlayer dielectric layer are formed over the isolation structure, and the cutting trench extends into the isolation structure.
6 . The method for forming the semiconductor structure as claimed in claim 1 , further comprising:
forming a second active region;
forming a dummy gate structure across the first active region and the second active region;
replacing a first portion of the dummy gate structure and a portion of the second active region with a fin cutting structure; and
replacing a second portion of the dummy gate structure with the gate stack, wherein the cutting trench exposes the fin cutting structure.
7 . The method for forming the semiconductor structure as claimed in claim 6 , wherein in a plan view, the first portion of the cutting trench includes a first protruding portion extending a first distance toward the first active region and a second protruding portion extending a second distance toward the second active region, and the second distance is longer than the first distance.
8 . The method for forming the semiconductor structure as claimed in claim 7 , wherein the second protruding portion is wider than the first protruding portion.
9 . A method for forming a semiconductor structure, comprising:
forming a first plurality of nanostructures over a lower fin element;
forming a source/drain feature over the lower fin element to abut the first plurality of nanostructures;
forming an interlayer dielectric layer over the source/drain feature;
forming a first gate stack to surround the first plurality of nanostructures;
forming a spacer layer between the first gate stack and the source/drain feature; and
forming a gate cutting structure in the spacer layer, the first gate stack and the interlayer dielectric layer, wherein the gate cutting structure includes a first protruding portion which extends a first distance from a first sidewall of the gate cutting structure toward the first plurality of nanostructures in a first direction that is parallel to a longitudinal axis of the first gate stack.
10 . The method for forming the semiconductor structure as claimed in claim 9 , wherein the gate cutting structure includes a second protruding portion which extends a second distance from the first sidewall of the gate cutting structure toward the first plurality of nanostructures in the first direction, and the second distance is shorter than the first distance.
11 . The method for forming the semiconductor structure as claimed in claim 9 , wherein the first plurality of nanostructures has a first dimension in a second direction that is parallel to a longitudinal axis of the lower fin element, the first protruding portion of the gate cutting structure has a second dimension in the second direction, and the second dimension is less than the first dimension.
12 . The method for forming the semiconductor structure as claimed in claim 11 , wherein the first gate stack has a third dimension in the second direction, and the second dimension is greater than the third dimension.
13 . The method for forming the semiconductor structure as claimed in claim 9 , further comprising:
forming a second plurality of nanostructures over the lower fin element, wherein in the first direction, a first dimension of the first plurality of nanostructures is smaller than a second dimension of the second plurality of nanostructures; and
forming a second gate stack to surround the second plurality of nanostructures.
14 . The method for forming the semiconductor structure as claimed in claim 13 , wherein the first sidewall of the gate cutting structure includes a portion facing the second plurality of nanostructures, and the portion of the first sidewall of the gate cutting structure is indented from the first sidewall of the gate cutting structure in the first direction.
15 . A method for forming a semiconductor structure, comprising:
forming a first plurality of channel layers over a first fin element;
forming a second plurality of channel layers over a second fin element;
forming a first source/drain feature over the first fin element;
forming a second source/drain feature over the second fin element;
forming a gate stack across the first fin element and the second fin element, wherein the gate stack wraps around the first plurality of channel layers and the second plurality of channel layers; and
forming a gate cutting structure through the gate stack, wherein:
the gate cutting structure has a first edge between the first plurality of channel layers and the second plurality of channel layers and a second edge between the first source/drain feature and the second source/drain feature, and
in a top view, the first edge is offset from the second edge by a distance, and the first edge is connected to the second edge through a third edge of the gate cutting structure.
16 . The method for forming the semiconductor structure as claimed in claim 15 , wherein the first edge and the second edge extend along a first direction, and the third edge extends along a second direction that is perpendicular to the first direction.
17 . The method for forming the semiconductor structure as claimed in claim 16 , wherein the first fin element and the second fin element extend lengthwise along the first direction, and the gate stack extends lengthwise along the second direction.
18 . The method for forming the semiconductor structure as claimed in claim 16 , wherein the first plurality of channel layers has a first dimension along the first direction, the first edge has a second dimension along the first direction, and the second dimension is less than the first dimension.
19 . The method for forming the semiconductor structure as claimed in claim 15 , further comprising:
forming an isolation structure between the first fin element and the second fin element, wherein the gate cutting structure vertically extends into the isolation structure.
20 . The method for forming the semiconductor structure as claimed in claim 15 , further comprising:
forming a contact plug on the first source/drain feature and the second source/drain feature, wherein the contact plug is located directly above the gate cutting structure.