IP Library Granted Patent US 12,048,161
Granted Patent B2
US 12,048,161 · App. 18/318,739 · Granted Jul 23, 2024

Electronic device having stacked structures and method for manufacturing the same

Inventors: Ki Hong Lee (Gyeonggi-do, KR); Ji Yeon Baek (Gyeonggi-do, KR); Seung Ho Pyi (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
H10B43/27H01L21/76898H10B43/10H10B43/35
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Quick Facts
Patent No.
US 12,048,161
App. No.
18/318,739
Granted
Jul 23, 2024
Kind
B2
Abstract

A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.

Claims (15)

1. An electronic device, comprising:

a first conductive layer including a trench and a partition portion surrounding the trench;

a second conductive layer formed in the trench;

a stacked structure including conductive layers and insulating layers which are alternately stacked over the second conductive layer, wherein the conductive layers and the insulating layers extend to cover the partition portion of the first conductive layer;

a channel layer passing through the stacked structure and including a contact surface connected to the second conductive layer; and

a memory layer between the channel layer and the stacked structure.

2. The electronic device of claim 1 , wherein the contact surface of the channel layer includes a bottom surface of the channel layer.

3. The electronic device of claim 1 , wherein the second conductive layer includes silicon.

4. The electronic device of claim 1 , wherein the second conductive layer includes a sidewall contacting the partition portion of the first conductive layer and a lowermost surface extending along a bottom of the trench.

5. The electronic device of claim 1 , further comprising a slit passing through the stacked structure,

wherein the trench and the second conductive layer extend to overlap with the slit.

6. The electronic device of claim 5 , further comprising a vertical insulating layer buried in a lower portion of the stacked structure,

wherein the vertical insulating layer includes an end portion overlapping with an edge of the slit and an extension portion overlapping with the partition portion of the first conductive layer.

7. The electronic device of claim 6 , wherein the conductive layers include lower selection gate electrodes partitioned by the vertical insulating layer, an upper selection gate electrode over the vertical insulating layer, and a memory cell gate electrode between the vertical insulating layer and the upper selection gate electrode, and

wherein the upper selection gate electrode and the memory cell gate electrode continuously extend to cover the lower selection gate electrodes.

Priority Claims (1)
KR 10-2014-0192025 · Dec 29, 2014 · national
Continuity (6)
Continuation 17151412 · Jan 18, 2021
Continuation 16298923 · Mar 11, 2019
Continuation 15821388 · Nov 22, 2017
Continuation 15398467 · Jan 4, 2017
Division 14732390 · Jun 5, 2015
Related Publication 20230292514A1 · Sep 14, 2023