Backside gate contact

1. A semiconductor structure, comprising:

a first gate structure partially disposed over an isolation structure;

a second gate structure partially disposed over the isolation structure;

a dielectric fin disposed directly on the isolation structure and in contact with a sidewall of the first gate structure and a sidewall of the second gate structure; and

a backside gate contact disposed below the first gate structure and adjacent to the isolation structure,

wherein a bottom surface of the first gate structure is in direct contact with the backside gate contact.

2. The semiconductor structure of claim 1 , further comprising:

a first dielectric liner disposed between the backside gate contact and the isolation structure.

3. The semiconductor structure of claim 2 , further comprising:

a second dielectric liner disposed below the second gate structure; and

a backside dielectric layer over the second dielectric liner.

4. The semiconductor structure of claim 3 , wherein the backside dielectric layer is spaced apart from the isolation structure by the second dielectric liner.

5. The semiconductor structure of claim 3 , wherein the first dielectric liner and the second dielectric liner comprise silicon nitride, silicon carbonitride, silicon oxycarbide, or silicon oxycarbonitride.

6. The semiconductor structure of claim 2 , further comprising:

a plurality of nanostructures,

wherein the first gate structure wraps around each of the plurality of nanostructures.

7. The semiconductor structure of claim 6 ,

wherein sidewalls of the plurality of nanostructures are in direct contact with a source/drain feature,

wherein the source/drain feature is spaced apart from the first gate structure by a plurality of inner spacer features.

8. The semiconductor structure of claim 7 , further comprising:

a dielectric plug disposed below the source/drain feature,

wherein a sidewall of the dielectric plug is spaced apart from a sidewall of the backside gate contact by the first dielectric liner.

9. The semiconductor structure of claim 1 , further comprising:

a first gate top metal layer over the first gate structure; and

a second gate top metal layer over the second gate structure.

10. The semiconductor structure of claim 9 , wherein the first gate top metal layer is spaced apart from the second gate top metal layer by a gate cut feature.

11. A semiconductor structure, comprising:

a first plurality of nano structures;

a second plurality of nano structures;

a source/drain feature disposed between the first plurality of nanostructures and the second plurality of nanostructures and in contact with sidewalls of the first plurality of nanostructures and the second plurality of nanostructures;

a dielectric plug disposed below the source/drain feature;

a first gate structure wrapping around each of the first plurality of nanostructures;

a second gate structure wrapping around each of the second plurality of nanostructures;

a backside gate contact disposed below and in contact with the first gate structure;

a first dielectric liner disposed between a sidewall of the backside gate contact and a first sidewall of the dielectric plug;

a backside dielectric layer disposed below the second gate structure; and

a second dielectric liner disposed between a sidewall of the backside dielectric layer and a second sidewall of the dielectric plug.

12. The semiconductor structure of claim 11 , wherein the dielectric plug comprises silicon nitride, silicon carbonitride, silicon oxycarbide, or silicon oxycarbonitride.

13. The semiconductor structure of claim 11 ,

wherein the first gate structure comprises a gate dielectric layer and a gate electrode layer,

wherein the backside gate contact extends through gate dielectric layer to contact the gate electrode layer.

14. The semiconductor structure of claim 11 , further comprising:

a first gate top metal layer over the first gate structure; and

a second gate top metal layer over the second gate structure.

15. The semiconductor structure of claim 14 , further comprising:

a frontside gate contact disposed over and in contact with the second gate top metal layer.

16. A method, comprising:

receiving a workpiece comprising:

first nanostructures disposed over a first mesa structure,

second nanostructure disposed over a second mesa structure,

a first gate structure wrapping around the first nanostructures;

a second gate structure wrapping around the second nanostructures,

a source/drain feature sandwiched between the first nanostructures and the second nanostructures, and

a sacrificial plug below the source/drain feature and between the first mesa structure and the second mesa structure,

flipping the workpiece upside down;

after the flipping, selectively removing the first mesa structure and the second mesa structure to form a first gate access opening over the first gate structure and a second gate access opening over the second gate structure;

depositing a dielectric liner over the first gate access opening and the second gate access opening;

depositing a backside dielectric layer over the dielectric liner;

planarizing the workpiece to expose the sacrificial plug;

selectively removing the sacrificial plug to form a backside source/drain opening to expose the source/drain feature;

depositing a dielectric plug over in the backside source/drain opening;

forming a backside gate access opening through the backside dielectric layer over the first gate structure; and

forming a backside gate contact in the backside gate access opening.

17. The method of claim 16 ,

wherein the first mesa structure and the second mesa structure comprise silicon,

wherein the sacrificial plug comprise silicon germanium.

18. The method of claim 16 , wherein the dielectric plug comprises silicon nitride, silicon carbonitride, silicon oxycarbide, or silicon oxycarbonitride.

19. The method of claim 16 , further comprising:

before the selective removing of the first mesa structure and the second mesa structure, forming a protective layer over the first mesa structure and the second mesa structure.

20. The method of claim 16 , wherein the dielectric liner comprises silicon nitride, silicon carbonitride, silicon oxycarbide, or silicon oxycarbonitride.