Image sensor scheme for optical and electrical improvement
The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate having a pixel region arranged between one or more trenches formed by sidewalls of the substrate. One or more dielectric materials are arranged along the sidewalls of the substrate forming the one or more trenches. A conductive material is disposed within the one or more trenches. The conductive material is electrically coupled to an interconnect disposed within a dielectric arranged on the substrate.
1. An integrated chip, comprising:
a substrate comprising a pixel region arranged between one or more trenches formed by sidewalls of the substrate;
one or more dielectric materials arranged along the sidewalls of the substrate forming the one or more trenches; and
a conductive material disposed within the one or more trenches, wherein the conductive material is electrically coupled to an interconnect disposed within a dielectric arranged on the substrate.
2. The integrated chip of claim 1 , further comprising:
one or more gate structures arranged along a front-side of the substrate, wherein the interconnect is arranged along a back-side of the substrate opposing the front-side of the substrate.
3. The integrated chip of claim 1 , wherein the one or more dielectric materials comprise a vertically extending segment extending along the sidewalls of the substrate and a horizontally extending segment extending along a back-side of the substrate, the vertically extending segment being continuous with the horizontally extending segment.
4. The integrated chip of claim 1 , wherein the conductive material continuously extends between outermost sidewalls of the conductive material along a horizontal plane extending through a vertical center of the conductive material.
5. The integrated chip of claim 1 , wherein the one or more dielectric materials comprise an outer sidewall facing the substrate, the outer sidewall having a curved segment.
6. The integrated chip of claim 1 , wherein the one or more dielectric materials have a thickness laterally between the conductive material and the substrate, the thickness varying over a height of the conductive material.
7. The image sensor-integrated chip of claim 1 , wherein the interconnect physically contacts the conductive material directly over the one or more trenches.
8. An integrated chip, comprising:
a substrate comprising a pixel region arranged between one or more trenches formed by sidewalls of the substrate, the one or more trenches extending from a back-side of the substrate to within the substrate;
one or more dielectric materials arranged along the sidewalls of the substrate forming the one or more trenches; and
a reflective material disposed within the one or more trenches, the reflective material having a height measured along a vertical line extending through a center of the reflective material, the height being larger than a maximum width of the reflective material measured along a horizontal line perpendicular to the vertical line.
9. The integrated chip of claim 8 , wherein the reflective material is a conductive material.
10. The integrated chip of claim 9 , wherein the conductive material is located at a lateral center and a vertical center of respective ones of the one or more trenches.
11. The integrated chip of claim 9 , wherein the conductive material has a curved outer surface facing the one or more dielectric materials.
12. The integrated chip of claim 9 , wherein the conductive material has a first width at a first distance from the back-side of the substrate and a second width at a second distance from the back-side of the substrate, the first distance being larger than the second distance and the first width being larger than the second width.
13. The integrated chip of claim 8 , wherein the one or more trenches respectively have a first width at a first distance from the back-side of the substrate and a second width at a second distance from the back-side of the substrate, the first distance being larger than the second distance and the first width being larger than the second width.
14. The integrated chip of claim 8 , wherein the reflective material continuously extends between opposing sides of the reflective material along a horizontal plane extending along the back-side of the substrate.
15. An integrated chip, comprising:
a substrate comprising a pixel region arranged between one or more trenches formed by sidewalls of the substrate;
one or more dielectric materials arranged along the sidewalls of the substrate forming the one or more trenches; and
a reflective material arranged within the one or more trenches between sidewalls of the one or more dielectric materials, wherein the reflective material is disposed within a central region of respective ones of the one or more trenches.
16. The integrated chip of claim 15 , wherein interior surfaces of the one or more dielectric materials form an air gap arranged within the one or more trenches between the interior surfaces of the one or more dielectric materials.
17. The integrated chip of claim 16 , wherein the air gap abuts the reflective material.
18. The integrated chip of claim 16 , wherein the air gap is filled with a gas.
19. The integrated chip of claim 16 , wherein the air gap has a first height and the reflective material has a second height, the second height being different than the first height.
20. The integrated chip of claim 15 , further comprising:
a diffusion barrier layer disposed within the one or more trenches and surrounding the reflective material.