Method and device for boosting performance of FinFETs via strained spacer
A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.
1. A structure, comprising:
an isolation structure;
a first dielectric fin, a second dielectric fin, and a third dielectric fin extending parallel to one another and vertically into the isolation structure;
a first semiconductor fin disposed in the isolation structure and between the first dielectric fin and the second dielectric fin;
a second semiconductor fin disposed in the isolation structure and between the second dielectric fin and the third dielectric fin;
a first source/drain feature disposed on the first semiconductor fin and partially in contact with the first dielectric fin and the second dielectric fin; and
a second source/drain feature disposed on the second semiconductor fin and spaced apart from the second dielectric fin and the third dielectric fin.
2. The structure of claim 1 ,
wherein the first source/drain feature is diamond-shaped,
wherein the second source/drain feature is bar-shaped.
3. The structure of claim 1 ,
wherein the first source/drain feature comprises silicon germanium and a p-type dopant,
wherein the second source/drain feature comprises silicon and an n-type dopant.
4. The structure of claim 1 , wherein each of the first semiconductor fin and the second semiconductor fin is spaced apart from the isolation structure by a fin spacer.
5. The structure of claim 4 , wherein the first source/drain feature and the second source/drain feature are disposed over a top surface of the fin spacer.
6. The structure of claim 1 , wherein the first dielectric fin, the dielectric second fin, and the third dielectric fin comprise silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), aluminum oxide (AlO 3 ), zirconium oxide (ZrO 2 ), yttrium oxide (Y 2 O 3 ), hafnium oxide (HfO 2 ), titanium oxide (TiO 2 ), or tantalum oxide (Ta 2 O 5 ).
7. The structure of claim 1 , wherein a base portion of the first source/drain feature is spaced apart from the first dielectric fin or the second dielectric fin by a first spacer and a second spacer.
8. The structure of claim 7 , wherein the second spacer is spaced apart from the first dielectric fin or the second dielectric fin by the first spacer.
9. The structure of claim 7 ,
wherein the first spacer comprises silicon carbonitride,
wherein the second spacer comprises silicon oxycarbonitride.
10. A semiconductor structure, comprising:
an isolation structure;
a first dielectric fin and a second dielectric fin extending parallel to one another and vertically into the isolation structure;
a semiconductor fin disposed in the isolation structure and between the first dielectric fin and the second dielectric fin; and
a first source/drain feature disposed on the semiconductor fin,
wherein the first source/drain feature is bar-shaped and comprises a bottom portion and a top portion over the bottom portion,
wherein the bottom portion is spaced apart from the first dielectric fin and the second dielectric fin by a first spacer and a second spacer,
wherein the top portion is spaced apart from the first dielectric fin and the second dielectric fin by the second spacer.
11. The semiconductor structure of claim 10 , wherein the first source/drain feature comprises silicon and an n-type dopant.
12. The semiconductor structure of claim 10 , wherein the first spacer comprises silicon carbonitride.
13. The semiconductor structure of claim 10 , wherein the second spacer comprises silicon nitride, silicon oxide, or hydrocarbon doped silicon nitride.
14. The semiconductor structure of claim 10 , wherein the first dielectric fin and the second dielectric fin comprise silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), aluminum oxide (AlO 3 ), zirconium oxide (ZrO 2 ), yttrium oxide (Y 2 O 3 ), hafnium oxide (HfO 2 ), titanium oxide (TiO 2 ), or tantalum oxide (Ta 2 O 5 ).
15. The semiconductor structure of claim 10 , wherein the second spacer comprises a dielectric constant between about 5 and about 6.
16. A method, comprising:
providing a workpiece, the workpiece comprising:
an isolation structure,
a first dielectric fin and a second dielectric fin sandwiching the isolation structure along a direction,
a fin disposed between the first dielectric fin and the second dielectric fin and extending partially into the isolation structure,
depositing a first spacer over the workpiece, including over the fin;
depositing a second spacer over the first spacer;
after the depositing of the second spacer, recessing the fin, the first spacer and the second spacer;
forming a bar-shaped source/drain feature over the fin;
after the forming of the bar-shaped source/drain feature, selectively recessing the second spacer; and
after the selectively recessing of the second spacer, depositing a third spacer over the first spacer, the bar-shaped source/drain feature, a top surface of the first dielectric fin, and a top surface of the second dielectric fin.
17. The method of claim 16 , wherein the forming of the bar-shaped source/drain feature comprises use of silane and hydrochloric acid.
18. The method of claim 16 , wherein the bar-shaped source/drain feature comprises silicon and an n-type dopant.
19. The method of claim 16 , further comprising:
after the depositing of the third spacer, performing an anneal process.
20. The method of claim 19 , wherein the anneal process comprises a temperature between about 700° C. and about 850° C.