Stacked integrated circuit devices
Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.
1. An integrated circuit device comprising:
a plurality of standard cells arranged on a substrate in multiple rows that each extend in a first direction, wherein the plurality of standard cells comprises a first standard cell in a first row and a second standard cell in a second row that is immediately adjacent to the first row,
wherein each of the first and second standard cells comprises:
an upper transistor comprising:
an upper active region;
an upper gate structure on the upper active region; and
an upper source/drain region on the upper active region;
a lower transistor between the substrate and the upper transistor, the lower transistor comprising:
a lower active region;
a lower gate structure on the lower active region; and
a lower source/drain region on the lower active region;
a first power line and a second power line;
a first power via electrically connecting the first power line to the lower source/drain region; and
a second power via electrically connecting the second power line to the upper source/drain region,
wherein, in the first standard cell, the upper transistor is between the lower transistor and the second power line, and
wherein the first power via of the first standard cell and the first power via of the second standard cell are aligned with each other along the first direction.
2. The integrated circuit device of claim 1 , wherein, in the first standard cell, the lower transistor is between the upper transistor and the first power line.
3. The integrated circuit device of claim 1 , wherein, in the first standard cell, the second power via vertically overlaps the first power via.
4. The integrated circuit device of claim 1 , wherein, in the first standard cell, the upper active region extends longitudinally in the first direction, and the upper gate structure is spaced apart from the upper source/drain region in the first direction.
5. The integrated circuit device of claim 1 , wherein the first standard cell and the second standard cell are the same kind of standard cell.
6. The integrated circuit device of claim 1 , wherein the first standard cell and the second standard cell are each an inverter.
7. The integrated circuit device of claim 1 , wherein the first power line of the first standard cell comprises a first portion of a shared power line, and the first power line of the second standard cell comprises a second portion of the shared power line, and
wherein the shared power line extends along an interface between the first row and the second row.
8. The integrated circuit device of claim 7 , wherein the first power via of the first standard cell contacts the shared power line and protrudes upward from the shared power line, and the first power via of the second standard cell contacts the shared power line and protrudes upward from the shared power line.
9. The integrated circuit device of claim 8 , wherein the first power via of the first standard cell contacts a center of the shared power line in a second direction that is perpendicular to the first direction, and the first power via of the second standard cell contacts the center of the shared power line in the second direction.
10. The integrated circuit device of claim 1 , wherein the upper source/drain region comprises a first upper source/drain region, and the lower source/drain region comprises a first lower source/drain region,
wherein each of the plurality of standard cells further comprises:
a second upper source/drain region on the upper active region;
a second lower source/drain region on the lower active region; and
an output via electrically connecting the second lower source/drain region to the second upper source/drain region, and
wherein the output via of the first standard cell and the first power via of the first standard cell are aligned with each other along the first direction.
11. The integrated circuit device of claim 1 , wherein the upper source/drain region comprises a first upper source/drain region, and the lower source/drain region comprises a first lower source/drain region,
each of the plurality of standard cells further comprises:
a second upper source/drain region on the upper active region;
a second lower source/drain region on the lower active region; and
an output via electrically connecting the second lower source/drain region to the second upper source/drain region, and
the output via of the first standard cell overlaps an interface between the first row and the second row.