Semiconductor memory devices with diode-connected MOS
A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.
1. A memory device, comprising:
a plurality of one-time-programmable (OTP) memory cells;
wherein each of the plurality of OTP memory cells comprises N first transistors, N second transistors, N third transistors, N diode-connected transistors, and a capacitor, N being a positive integer; and
wherein each of the N first transistors is coupled to a respective one of the N second transistors, a respective one of the N third transistors, and a respective one of the M diode-connected transistors in series, with one terminal of the capacitor connected to a node between the respective second transistor and the respective third transistor.
2. The memory device of claim 1 , wherein the other terminal of the capacitor is connected to a bit line (BL) configured to provide a programming voltage.
3. The memory device of claim 1 , wherein gate terminals of the N diode-connected transistors are commonly coupled to the BL.
4. The memory device of claim 1 , wherein a voltage drop across the capacitor is inversely proportional to a number of the N third transistors being activated.
5. The memory device of claim 1 , wherein gate terminals of the N first transistors are commonly coupled to a word line (WL), gate terminals of the N second transistors are commonly coupled to a first control line (CL 1 ), and gate terminals of the N first transistors are respectively coupled to respective different second control lines (CL 2 ).
6. The memory device of claim 5 , wherein gate terminals of the N diode-connected transistors are commonly coupled to either the WL or the CL 1 .
7. The memory device of claim 1 , wherein the N first transistors, the N second transistors,
the N third transistors, and the N diode-connected transistors are each an n-type transistor.
8. The memory device of claim 1 , wherein the N first transistors, the N second transistors, and the N third transistors are each an n-type transistor, and the N diode-connected transistors are each a p-type transistor.
9. A memory device, comprising:
a plurality of memory cells arranged along a column of a memory array;
wherein each of the plurality of memory cells comprises N cell-rows, each of the N cell-rows comprising a first transistor, a second transistor, N third transistors, a diode-connected transistor, N being a positive integer; and
wherein the N cell-rows are commonly connected to a capacitor.
10. The memory device of claim 9 , wherein each of the memory cells is configured as a one-time-programmable (OTP) memory cell.
11. The memory device of claim 9 , wherein, within each of the N cell-rows, the first transistor, the second transistor, the N third transistors, and the diode-connected transistor are connected in series, with one terminal of the capacitor connected to a node between the second transistor and the third transistor.
12. The memory device of claim 11 , wherein the other terminal of the capacitor is connected to a bit line (BL) configured to provide a programming voltage.
13. The memory device of claim 9 , wherein a voltage drop across the capacitor is inversely proportional to a number of the N third transistors being activated.
14. The memory device of claim 9 , wherein gate terminals of the first transistors of the N cell-rows are commonly coupled to a word line (WL), gate terminals of the second transistors of the N cell-rows are commonly coupled to a first control line (CL 1 ).
15. The memory device of claim 9 , wherein gate terminals of the N first transistors of each of the N cell-rows are respectively coupled to respective different second control lines (CL 2 ).
16. The memory device of claim 9 , wherein the first transistor, the second transistor, the N third transistors, and the diode-connected transistor are each an n-type transistor.
17. The memory device of claim 9 , wherein the first transistor, the second transistor, and the N third transistors are each an n-type transistor, and the diode-connected transistors is a p-type transistor.
18. A memory device, comprising:
a plurality of memory cells arranged along a column of a memory array;
wherein each of the plurality of memory cells comprises N cell-rows, each of the N cell-rows comprising a first transistor, a second transistor, N third transistors, a diode-connected transistor, N being a positive integer;
wherein the N cell-rows are commonly connected to a capacitor;
wherein, within each of the N cell-rows, the first transistor, the second transistor, the N third transistors, and the diode-connected transistor are connected in series, with one terminal of the capacitor connected to a node between the second transistor and the third transistor; and
wherein the other terminal of the capacitor is connected to a bit line (BL) configured to provide a programming voltage.
19. The memory device of claim 18 , wherein each of the memory cells is configured as a one-time-programmable (OTP) memory cell.
20. The memory device of claim 18 , wherein a voltage drop across the capacitor is inversely proportional to a number of the N third transistors being activated.