Granted Patent B2

US 12,648,165 · App. 18/328,182 · Granted Jun 2, 2026

Inventors: Abhitosh Vais (Heverlee, BE); Bertrand Paravais (Nil-Saint-Vincent, BE); Guillaume Boccardi (Sint-Lambrechts-Woluwe, BE); Bernardette Kunert (Wilsele, BE); Yves Mols (Wijnegem, BE); Sachin Yadav (Leuven, BE)

Assignee: Imec vzw

H10D10/80H10D30/47H10P54/00H10W20/023H10W80/312H10W80/327

Abstract

Claims (51)

1 . A method for producing a semiconductor chip comprising the steps of:

providing a first semiconductor substrate including a support layer arranged thereon, the support layer comprising at least one cavity that is open through a surface of the support layer, with a semiconductor material of the first semiconductor substrate exposed on a bottom of the cavity;

producing a multilayer structure on the first semiconductor substrate and extending outward from the surface of the support layer, by growing consecutive layers in the at least one cavity and subsequently out of the at least one cavity, the multilayer structure comprising:

at least one first semiconductor layer grown upwards from the bottom of the cavity;

a release layer, on the at least one first semiconductor layer;

one or more additional semiconductor layers on the release layer, wherein at least the one or more additional semiconductor layers above the release layer are essentially defect-free layers;

producing a dielectric template layer on the support layer, wherein:

the dielectric template layer comprises a first sublayer directly on the support layer, the first sublayer being formed of a first dielectric material, and a second sublayer directly on the first sublayer, and formed of a second dielectric material different from the first dielectric material;

the first sublayer and the second sublayer are formed before or after producing the multilayer structure;

the dielectric template layer is directly adjacent and in contact with the multilayer structure, leaving a top layer of the multilayer structure exposed;

the first dielectric material is etchable selectively with respect to the second dielectric material, the multilayer structure and the support layer;

at least one of the bottom and top surface of the release layer is positioned between the bottom and top surface of the first sublayer of the dielectric template layer;

after the formation of the multilayer structure and the dielectric template layer, producing at least one semiconductor device from one or more additional semiconductor layers positioned above the release layer;

after producing the at least one semiconductor device, producing electrically conductive paths and a plurality of first contact pads, so that the conductive paths couple the at least one semiconductor device to the first contact pads, the first contact pads being part of a planar hybrid bonding surface formed of the first contact pads and of a first dielectric bonding layer produced on the second sublayer of the dielectric template layer;

providing a second semiconductor substrate, comprising a front end of line portion comprising further semiconductor devices, and a back end of line portion, the back end of line portion comprising a plurality of second contact pads, the plurality of second contact pads being part of a second planar hybrid bonding surface formed of the plurality of second contact pads and of a second dielectric bonding layer that is part of the back end of line portion;

performing hybrid bonding of the first semiconductor substrate to the second semiconductor substrate by mutually bonding the first dielectric and second dielectric bonding surfaces, so that the plurality of first contact pads are bonded and electrically connected to the plurality of second contact pads, thereby forming a bonded wafer assembly;

after the hybrid bonding process, producing a plurality of through semiconductor via openings through the second semiconductor substrate, starting from the back of the semiconductor second substrate and traversing the full thickness of the second sublayer of the dielectric template layer;

after producing the TSV openings, removing the first sublayer of the dielectric template layer selectively with respect to the second sublayer and with respect to the support layer and the multilayer structure, by supplying an etchant that removes the first sublayer selectively with respect to the multilayer structure and with respect to the second sublayer;

after removing the first sublayer, removing the release layer by supplying an etchant that removes the release layer selectively with respect to the other layers of the multilayer structure and with respect to the second sublayer and the support layer, thereby releasing the semiconductor second substrate and the device from the first semiconductor substrate, leaving a backside of the device exposed, wherein at least one of the etchants is supplied through the TSV openings;

after releasing the second semiconductor substrate, filling the TSV openings with an electrically conductive material; and

singulating the second semiconductor substrate to thereby obtain a semiconductor chip comprising the device formed of layers of the multilayer structure, integrated with the devices in the front end of line portion.

2 . The method of claim 1 , wherein the cavity is a trench and wherein the multilayer structure is a nano-ridge structure obtained by growing a first layer in the trench, the width of the trench being suitable for applying aspect ratio trapping.

3 . The method of claim 2 , wherein the first semiconductor substrate is a silicon or a germanium substrate and wherein the nano-ridge structure is formed of layers of group III-V semiconductor material.

4 . The method of claim 1 , wherein the first layer grown directly on the bottom of the cavity is essentially matching the first semiconductor substrate in terms of the respective lattice constants and thermal expansion coefficients of the first layer and of the first substrate.

5 . The method of claim 4 , wherein the first semiconductor substrate is a germanium substrate, and wherein the multilayer structure is formed of layers of group III-V semiconductor material, or wherein the multilayer structure comprises a Ge layer directly on the Ge substrate, a group III-V release layer and one or more group IV semiconductor layers on the release layer.

6 . The method of claim 5 , wherein at least the first sublayer of the dielectric template layer is produced prior to growing the multilayer structure, and patterned so as to form sidewalls aligned to at least two opposite edges of the cavity so that the growth of the multilayer structure outside of the cavity is laterally contained by the sidewalls.

7 . The method of claim 1 , wherein at least the first sublayer of the dielectric template layer is produced prior to growing the multilayer structure, and patterned so as to form sidewalls aligned to at least two opposite edges of the cavity so that the growth of the multilayer structure outside of the cavity is laterally contained by the sidewalls.

8 . The method of claim 3 , wherein at least the first layer of the template layer is produced prior to growing the multilayer structure, and patterned so as to form sidewalls aligned to at least two opposite edges of the cavity so that the growth of the multilayer structure outside of the cavity is laterally contained by the sidewalls.

9 . The method of claim 1 , wherein the dielectric template layer is produced after the formation of the multilayer structure, by producing the first sublayer on the support layer after the structure has been produced, and by producing the second sublayer on the first sublayer.

10 . The method of claim 5 , wherein the dielectric template layer is produced after the formation of the multilayer structure, by producing the first sublayer on the support layer after the structure has been produced, and by producing the second sublayer on the first sublayer.

11 . The method of claim 1 , wherein the at least one semiconductor device is a heterojunction bipolar transistor (HBT) formed on at least one multilayer structure, and comprising a collector layer, a base layer and an emitter layer.

12 . The method according to claim 11 , wherein an HBT is formed on an array of directly adjacent and parallel multilayer structures comprising the same layer sequence, and wherein the method comprises the steps of:

exposing a portion of the base layers of the array of multilayer structures, by removing portions of the layers present on top of the base layers;

epitaxially growing the material of the base layers on the exposed portions of the base layers, until the material merges in the areas between the nano-ridge structures, thereby forming base contact portions at least in between the nano-ridge structures;

producing conductive paths which are electrically connected to the base contact portions and to contact pads which are coplanar with the first bonding surface;

for each structure of the array of multilayer structures, producing a conductive path that is electrically connected to the remaining portion of the layers present on top of the base layer and to a contact pad that is coplanar with the first bonding surface;

bonding the contact pads to respective contact pads which are coplanar with the second bonding surface.

13 . The method of claim 1 , wherein the at least one semiconductor device is a high electron mobility transistor (HEMT) formed on one multilayer structure and comprising a channel layer and at least one barrier layer.

14 . The method of claim 1 , further comprising, after releasing and before singulating the second semiconductor substrate, the step of producing electrical connections to one or more layers of the released device, possibly after thinning and/or patterning the one or more layers.

15 . The method of claim 5 , further comprising, after releasing and before singulating the second semiconductor substrate, the step of producing electrical connections to one or more layers of the released device, possibly after thinning and/or patterning the one or more layers.

16 . A semiconductor chip produced according to the method of claim 1 , the semiconductor chip further comprising:

a carrier substrate corresponding to the first semiconductor substrate;

a front end of line (FEOL) portion above the carrier substrate;

a back end of line portion above the FEOL portion and comprising a top layer comprising the first contact pads;

wherein the second contact pads are bonded and thereby electrically connected to the first contact pads;

conductive paths connected to the second contact pads;

wherein the second semiconductor device is located above the back end of line portion and coupled to the conductive paths.

17 . The chip of claim 16 , wherein the semiconductor device is a group III-V device or a group IV device and wherein the carrier substrate is a silicon substrate.

18 . The chip of claim 17 wherein the semiconductor device is a HBT or a HEMT.

19 . The chip of claim 16 wherein the semiconductor device is a HBT or a HEMT.

20 . The chip of claim 19 comprising multiple of the devices, including at least one HBT and at least one HEMT.

Assignments (1)

Continuity (1)

References Cited (26)