IP Library › Granted Patent US 12,554,507
Granted Patent B2
US 12,554,507 · App. 18/328,688 · Granted Feb 17, 2026

Systems and methods for processing formatted data in computational storage

Inventors: Jonghyeon Kim (San Jose, CA); Soogil Jeong (Pleasanton, CA)
Assignee: Samsung Electronics Co., Ltd.
G06F9/3885G06F9/30007
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Quick Facts
Patent No.
US 12,554,507
App. No.
18/328,688
Granted
Feb 17, 2026
Kind
B2
Abstract

Provided is a method for performing computations near memory. The method includes receiving, at a storage device, first data associated with a first data set, the first data having a first format. The method further includes receiving, at a processor core of the storage device, a request to perform a function on the first data, the function including a first operation and a second operation. The method further includes performing, by a first processor-core acceleration engine of the storage device, the first operation on the first data, based on first processor-core custom instructions, to generate first result data. The method further includes performing, by a first extra-processor-core circuit of the storage device, the second operation on the first result data, based on the first processor-core custom instructions.

Claims (71)

1 . A method for performing computations, the method comprising:

receiving, at a storage device, first data comprising first page data corresponding to a first database page, and associated with a first data set, the first data having a first format;

receiving, at a processor core of the storage device, a request to perform a function on the first data, the function comprising a first operation and a second operation;

performing, by a first acceleration engine of the processor core, the first operation on the first data, based on first instructions stored on the processor core, to generate first result data; and

performing, by a first circuit of the storage device that is external to the processor core, the second operation on the first result data, based on the first instructions, the first circuit comprising a first scan engine, wherein:

the first operation comprises a decoding operation for determining the first format based on the first page data or a page rule-checking operation; and

the first result data comprises column data extracted, by the first acceleration engine, from the first page data.

2 . The method of claim 1 , wherein the storage device is configured to receive the request to perform the function via a communication protocol.

3 . The method of claim 1 , wherein:

the storage device comprises a scheduler;

the first circuit comprises the first scan engine and a second scan engine; and

the scheduler causes:

the first scan engine to perform the second operation on a first portion of a column associated with the column data; and

the second scan engine to perform the second operation on a second portion of the column.

4 . The method of claim 1 , further comprising:

receiving, at the storage device, second data associated with a second data set, the second data having a second format;

receiving a request to perform the function on the second data; and

performing, by a second acceleration engine of the processor core, the first operation on the second data, based on at least one second instruction stored on the processor core, to generate second result data.

5 . The method of claim 4 , further comprising performing, by the first circuit of the storage device, the second operation on the second result data, based on the at least one second instruction.

6 . The method of claim 1 , wherein:

the request is received via an application programming interface (API) of the storage device; and

the second operation is a scan operation.

7 . A system for performing computations, the system comprising:

a processor core storing first instructions and comprising a first acceleration engine of the processor core; and

a first circuit of the system that is external to the processor core and communicatively coupled to the processor core, the first circuit comprising a first scan engine,

wherein the processor core is implemented in hardware and is configured to:

receive first data comprising first page data corresponding to a first database page, and associated with a first data set, the first data having a first format;

receive a request to perform a function on the first data, the function comprising a first operation and a second operation;

cause the first acceleration engine to perform the first operation on the first data, based on the first instructions, to generate first result data; and

cause the first circuit to perform the second operation on the first result data, based on the first instructions, and

wherein:

the first operation comprises a decoding operation for determining the first format based on the first page data or a page rule-checking operation; and

the first result data comprises column data extracted, by the first acceleration engine, from the first page data.

8 . The system of claim 7 , wherein the processor core is configured to receive the request to perform the function via a communication protocol.

9 . The system of claim 7 , further comprising a scheduler coupled to the processor core, wherein:

the first circuit comprises the first scan engine and a second scan engine; and

the scheduler causes:

the first scan engine to perform the second operation on a first portion of a column associated with the column data; and

the second scan engine to perform the second operation on a second portion of the column.

10 . The system of claim 7 , wherein the processor core is configured to:

receive second data associated with a second data set, the second data having a second format;

receive a request to perform the function on the second data; and

cause a second acceleration engine of the processor core to perform the first operation on the second data, based on at least one second instruction stored on the processor core, to generate second result data.

11 . The system of claim 10 , wherein the processor core is configured to cause the first circuit to perform the second operation on the second result data, based on the at least one second instruction.

12 . The system of claim 7 , wherein:

the request is received via an application programming interface (API) coupled to the processor core; and

the second operation is a scan operation.

13 . A storage device for performing computations, the storage device comprising:

a processor core storing first instructions and comprising a first acceleration engine; and

a first circuit of the storage device that is external to the processor core and communicatively coupled to the processor core, the first circuit comprising a first scan engine,

wherein the processor core is implemented in hardware and is configured to:

receive first data comprising first page data corresponding to a first database page, and associated with a first data set, the first data having a first format;

receive a request to perform a function on the first data, the function comprising a first operation and a second operation;

cause the first acceleration engine to perform the first operation on the first data, based on the first instructions, to generate first result data; and

cause the first circuit to perform the second operation on the first result data, based on the first instructions, and

wherein:

the first operation comprises a decoding operation for determining the first format based on the first page data or a page rule-checking operation; and

the first result data comprises column data extracted, by the first acceleration engine, from the first page data.

14 . The storage device of claim 13 , further comprising a scheduler coupled to the processor core, wherein:

the first circuit comprises the first scan engine and a second scan engine; and

the scheduler causes:

the first scan engine to perform the second operation on a first portion of a column associated with the column data; and

the second scan engine to perform the second operation on a second portion of the column.

15 . The storage device of claim 13 , wherein the processor core is configured to:

receive second data associated with a second data set, the second data having a second format;

receive a request to perform the function on the second data; and

cause a second acceleration engine of the processor core to perform the first operation on the second data, based on at least one second instruction stored on the processor core, to generate second result data.

16 . The storage device of claim 15 , wherein the processor core is configured to cause the first circuit that is external to the processor core to perform the second operation on the second result data, based on the at least one second instruction.

17 . The storage device of claim 13 , wherein:

the request is received via an application programming interface (API) coupled to the processor core; and

the second operation is a scan operation.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2025
From: KIM, JONGHYEON; JEONG, SOOGIL
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 073236/0685 →
Continuity (3)
Provisional Application 63458608 · Apr 11, 2023
Provisional Application 63458618 · Apr 11, 2023
Related Publication 20240345843A1 · Oct 17, 2024
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