Semiconductor device having a metal pad and a protective layer for corrosion prevention due to exposure to halogen
Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method includes depositing a first dielectric layer over a metal pad disposed over a workpiece, forming a first opening in the first dielectric layer to expose a portion of the metal pad, after the forming of the first opening, forming a second dielectric layer over the exposed portion of the metal pad, depositing a first polymeric material over the second dielectric layer, forming a second opening through the first polymeric material and the second dielectric layer to expose the metal pad, and forming a bump feature over the exposed metal pad.
1. A semiconductor device, comprising:
a metal pad over a substrate;
a first dielectric layer disposed directly on the metal pad;
a second dielectric layer disposed over the first dielectric layer;
a protective layer disposed over the second dielectric layer and the metal pad;
a polymeric material disposed over the protective layer; and
a bump feature extending through the polymeric material and in direct contact with the metal pad, the polymeric material and the protective layer,
wherein a portion of the protective layer is in direct contact with a top surface of the metal pad.
2. The semiconductor device of claim 1 , wherein the metal pad comprises aluminum or an aluminum alloy.
3. The semiconductor device of claim 1 , wherein the first dielectric layer comprises undoped silicate glass.
4. The semiconductor device of claim 1 , wherein the second dielectric layer comprises silicon nitride.
5. The semiconductor device of claim 1 , wherein the protective layer is in contact with sidewalls of the first dielectric layer and the second dielectric layer.
6. The semiconductor device of claim 1 , wherein the polymeric material comprises halogen.
7. The semiconductor device of claim 6 , wherein the polymeric material comprises fluorine or chlorine.
8. A semiconductor structure, comprising:
a passivation structure;
a passive device disposed in the passivation structure;
a contact via extending through the passivation structure and the passive device;
a metal pad disposed over the passivation structure and electrically coupled to the contact via;
a first dielectric layer disposed directly on the metal pad;
a second dielectric layer disposed over the first dielectric layer;
a protective layer disposed over the second dielectric layer;
a polymeric material disposed over the protective layer; and
a bump feature extending through the polymeric material and in direct contact with the metal pad, the polymeric material and the protective layer.
9. The semiconductor structure of claim 8 , wherein the protective layer is in contact with a top surface of the metal pad.
10. The semiconductor structure of claim 8 , wherein the polymeric material is spaced apart from the first dielectric layer and the second dielectric layer by the protective layer.
11. The semiconductor structure of claim 8 , wherein the passive device comprises an metal-insulator-metal (MIM) structure.
12. The semiconductor structure of claim 8 , wherein the metal pad comprises aluminum.
13. The semiconductor structure of claim 8 , wherein the first dielectric layer is in contact with a top surface of the passivation structure and sidewalls of the metal pad.
14. The semiconductor structure of claim 8 , wherein the polymeric material comprises CF 3 functional groups.
15. The semiconductor structure of claim 8 , wherein the bump feature comprises:
a metallization layer;
a bump layer over the metallization layer; and
a solder layer over the bump layer.
16. The semiconductor structure of claim 15 ,
wherein the metallization layer and the bump layer comprise copper,
wherein a copper content of the bump layer is greater than a copper content of the metallization layer.
17. A semiconductor structure, comprising:
an aluminum-containing metal pad over a substrate;
a first dielectric layer disposed directly on the aluminum-containing metal pad;
a second dielectric layer disposed over the first dielectric layer;
a protective layer disposed over the second dielectric layer and the aluminum-containing metal pad;
a polymeric material disposed over the protective layer; and
a bump feature extending through the polymeric material and in direct contact with the aluminum-containing metal pad, the polymeric material and the protective layer,
wherein the polymeric material is spaced apart from a top surface of the aluminum-containing metal pad by the protective layer,
wherein sidewalls of the first dielectric layer and the second dielectric layer are spaced apart from the bump feature by the protective layer and the polymeric material.
18. The semiconductor structure of claim 17 , wherein the protective layer comprises a thickness between about 50 Å and about 200 Å.
19. The semiconductor structure of claim 17 , wherein the polymeric material comprises fluorine or chlorine.
20. The semiconductor structure of claim 17 , wherein the protective layer comprises silicon oxide or silicon nitride.