Granted Patent B2

US 12,557,394 · App. 18/333,405 · Granted Feb 17, 2026

Inventors: Han-Chung Chang (Hsinchu, TW); Kuang-Ching Chang (Hsinchu, TW); Jia-Hong Gao (Hsinchu, TW); Po-Chih Cheng (Hsinchu, TW); Hui-Zhong Zhuang (Hsinchu, TW)

Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

H10D89/10H10D30/027H10D64/01H10D84/40H10D84/859

Abstract

Claims (87)

1 . A cell region of a semiconductor device, the cell region comprising:

active regions (ARs) formed as predetermined shapes on a substrate including:

first and second ARs having a first shape and correspondingly first and second dopant types;

a third AR having a second shape and the second dopant type; and

a fourth AR having a third shape and the first dopant type;

the first and second ARs being arranged in a first area of the cell region;

the third and fourth ARs being arranged in a second area of the cell region;

the second area being adjacent to the first area relative to a first direction;

the first shape being smaller than the second shape; and

the second shape being smaller than the third shape.

2 . The device of claim 1 , wherein:

the first direction is perpendicular to long axes correspondingly of the ARs.

3 . The device of claim 2 , wherein:

relative to the first direction, the first area shares a border with the second area.

4 . The device of claim 2 , wherein:

relative to the first direction, a border of the first area is separated from a border of the second area by a dummy region.

5 . The device of claim 1 , wherein:

the first direction is parallel to long axes correspondingly of the ARs.

6 . The device of claim 5 , wherein:

relative to the first direction, a border of the first area is separated from a border of the second area by a dummy region.

7 . The device of claim 6 , wherein:

the active regions (ARs) further include:

fifth and sixth ARs having the first shape and correspondingly the first and second dopant types; and

relative to a second direction perpendicular to the first direction,

the first and second ARs are stacked as a first unit and the fifth and sixth ARs are stacked as a second unit, and

the second unit is stacked on the first unit.

8 . The device of claim 1 , wherein:

the ARs further include:

a fifth AR having the second shape and the second dopant type; and

the fifth AR as well as the third and fourth ARs are arranged in the second area.

9 . The device of claim 8 , wherein:

relative to a second direction that is parallel to long axes correspondingly of the ARs, the fourth AR is between the third AR and the fifth AR.

10 . A cell region of a semiconductor device, the cell region comprising:

active regions (ARs) formed as predetermined shapes on a substrate including:

first and second ARs having a first shape and correspondingly first and second dopant types;

third and fourth ARs having a second shape and correspondingly the first and second dopant types;

the first and second ARs being arranged in a first area of the cell region;

the third and fourth ARs being arranged in a second area of the cell region;

the second area being adjacent to the first area relative to a first direction;

the first shape being smaller than the second shape.

11 . The device of claim 10 , wherein:

the first direction is perpendicular to long axes correspondingly of the ARs.

12 . The device of claim 11 , wherein:

relative to the first direction, a border of the first area is separated from a border of the second area by a dummy region.

13 . The device of claim 10 , wherein:

the first direction is parallel to long axes correspondingly of the ARs.

14 . The device of claim 13 , wherein:

relative to the first direction, a border of the first area is separated from a border of the second area by a dummy region.

15 . A method of forming semiconductor device, the method comprising:

forming active regions having predetermined shapes on a substrate including:

configuring a first area to include first and second ARs having a first shape;

configuring a second area to be adjacent to the first area relative to a first direction and to include third AR having a second shape and a fourth AR having a third shape,

the first shape being smaller than the second shape, and

the second shape being smaller than the third shape;

doping the ARs including:

doping the first and fourth ARs with a first dopant type; and

doping the second and third ARs with a second dopant type;

forming source/drain (S/D) regions including doping first areas of the active regions, the S/D regions representing first transistor-components, wherein second areas of the active regions which are between corresponding S/D regions are channel regions representing second transistor-components;

forming gate lines over corresponding ones of the channel regions, the gate lines representing third transistor-components; and

forming metal-to-S/D (MD) contact structures over corresponding ones of the S/D regions, the MD contact structures representing fourth transistor-components; and

the forming active regions, the doping the ARs, the forming S/D regions, the forming MD contact structures and the forming gate lines resulting in corresponding transistors.

16 . The method of claim 15 , wherein:

the forming active regions, the forming S/D regions, the forming MD contact structures and the forming gate lines further resulting in:

a first set of the first to fourth transistor-components connected as corresponding one of the transistors that define a primary latch;

a second set of the first to fourth transistor-components connected as corresponding one of the transistors that define a secondary latch; and

a third set of the first to fourth transistor-components connected as corresponding transistors that define a clock buffer;

a fourth set of the first to fourth transistor-components connected as corresponding ones of the transistors that define an output buffer;

the primary latch, the secondary latch, the output buffer and the clock buffer comprise a D flip-flop (DFF);

the primary latch includes a first sleepy inverter and a first non-sleepy (NS) inverter;

the secondary latch includes a second sleepy inverter and a second NS inverter; and

the clock buffer includes first and second NS inverters;

a first group of some but not all of the transistors being in the first area; and

ones of the transistors which comprise the output buffer being in the second area.

17 . The method of claim 16 , wherein:

ones of the transistors which comprise the first non-sleepy (NS) inverter are in the second area; and

ones of the transistors which comprise the second NS inverter are in the second area.

18 . The method of claim 16 , wherein:

the forming active regions, the forming S/D regions, the forming MD contact structures and the forming gate lines further results in a fifth set of the first to fourth transistor-components connected as corresponding ones of the transistors that define an internal buffer;

the internal buffer is included in the D flip-flop (DFF); and

ones of the transistors which comprise the internal buffer are in the second area.

19 . The method of claim 16 , wherein:

the forming active regions, the forming S/D regions, the forming MD contact structures and the forming gate lines further results in a fifth set of the first to fourth transistor-components connected as corresponding ones of the transistors that define a scan buffer; and

ones of the transistors which comprise the scan buffer are in the second area.

20 . The method of claim 16 , wherein:

the forming active regions, the forming S/D regions, the forming MD contact structures and the forming gate lines further results in a fifth set of the first to fourth transistor-components connected as corresponding ones of the transistors that define a multiplexer; and

first ones of the transistors which comprise the multiplexer are in the first area; and

second ones of the transistors which comprise the multiplexer are in the second area.

Assignments (1)

Continuity (2)

References Cited (22)