Method for generating layout diagram including protruding pin cell regions and semiconductor device based on same

1. A method of generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium, the method comprising:

generating a cell which represents a circuit, the cell including:

first and second side boundaries which are substantially parallel and extend in a first direction;

a first wiring pattern which is an intra-cell wiring pattern that extends in a second direction and represents a conductor of a first signal which is internal to the circuit, the second direction being substantially perpendicular to the first direction;

a second wiring pattern which extends in the first direction and represents a conductor of a second signal of the circuit;

configuring the intra-cell wiring pattern so that a first end thereof is located substantially a minimum boundary offset interior to the first side boundary; and

configuring the second wiring pattern so that a portion thereof has a first end which extends exterior to the first side boundary by a protrusion length which is substantially greater than the minimum boundary offset.

2. The method of claim 1 , wherein:

the minimum boundary offset is substantially half of a minimum end-to-end spacing for substantially collinear wiring patterns.

3. The method of claim 1 , further comprising:

configuring the second wiring pattern to leave a gap between a second end thereof and the second side boundary, a size of the gap in the second direction being substantially greater than the minimum boundary offset.

4. The method of claim 3 , further comprising:

substantially filling the gap with a dummy pattern;

configuring the dummy pattern so that a first end thereof substantially abuts a second end of the second wiring pattern; and

further configuring the dummy pattern so that a second end thereof is located substantially the minimum boundary offset interior to the second side boundary.

5. The method of claim 1 , further comprising:

further configuring the intra-cell wiring pattern so that a second end of the intra-cell wiring pattern is located substantially the minimum boundary offset from the second side boundary of the cell.

6. The method of claim 1 , further comprising:

further configuring the intra-cell wiring pattern to leave a gap between a second end of the intra-cell wiring pattern and the second side boundary of the cell, a size of the gap in the second direction being substantially greater than the minimum boundary offset.

7. The method of claim 1 , wherein:

the intra-cell wiring pattern is a first intra-cell wiring pattern; and

the method further comprises:

adding, to the cell, a third wiring pattern which is a second intra-cell wiring pattern and which extends in the second direction; and

adding, to the cell, a cut pattern which extends in the first direction and which, in effect, divides the second intra-cell wiring pattern into first and second portions.

8. The method of claim 1 , wherein one of the following is true:

the second wiring pattern is a pin pattern which extends in the first direction and further represents an input/output (I/O) terminal of the circuit; or

the second wiring pattern is a trans-boundary intra-cell wiring pattern.

9. The method of claim 1 , further comprising:

fabricating, based on the layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor device.

10. A semiconductor device comprising:

a cell region which includes components representing a circuit, the components being arranged such that a virtual perimeter is drawable around substantially all of the components, the virtual perimeter being rectangular and including:

first and second virtual side boundaries which are substantially parallel and extend in a first direction;

wherein the components of the cell region include:

a first conductor which is an intra-cell conductor of a first signal which is internal to the circuit;

the intra-cell conductor extending in a second direction, the second direction being substantially perpendicular to the first direction; and

a first end of the intra-cell conductor being located substantially a minimum virtual boundary offset interior to the first virtual side boundary; and

a second conductor of a second signal of the circuit;

the second conductor extending in the first direction; and

a portion of the second conductor having a first end which extends exterior to the first virtual side boundary by a protrusion length which is substantially greater than the minimum virtual boundary offset.

11. The semiconductor device of claim 10 , wherein:

the minimum virtual boundary offset is substantially half of a minimum virtual end-to-end spacing for substantially collinear conductors.

12. The semiconductor device of claim 10 , wherein:

a second end of the intra-cell conductor is located substantially the minimum virtual boundary offset from the second virtual side boundary of the cell region.

13. The semiconductor device of claim 10 , wherein:

the second conductor has a length in the second direction which results in a gap between a second end of the second conductor and the second virtual side boundary, a size of the gap in the second direction being substantially greater than the minimum virtual boundary offset; and

the components of the cell region further include:

a dummy structure which is substantially collinear with the second conductor and which substantially fills the gap;

a first end of the dummy structure substantially abutting a second end of the second conductor; and

a second end of the dummy structure being located substantially the minimum virtual boundary offset interior to the second virtual side boundary.

14. The semiconductor device of claim 10 , wherein:

the intra-cell conductor has a length in the second direction which results in a gap between a second end of the intra-cell conductor and the second virtual side boundary of the cell region, a size of the gap in the second direction being substantially greater than the minimum virtual boundary offset; and

the components of the cell region further include:

a dummy structure which is substantially collinear with the intra-cell conductor and which substantially fills the gap;

a first end of the dummy structure substantially abutting a second end of the intra-cell conductor; and

a second end of the dummy structure being located substantially the minimum virtual boundary offset interior to the second virtual side boundary.

15. A method of generating a layout diagram, the layout diagram being stored on a non-transitory computer-readable medium, the method comprising:

generating a cell which represents a circuit, the cell including:

first and second side boundaries which are substantially parallel and extend in a first direction;

a first wiring pattern which is an intra-cell wiring pattern that extends in a second direction and represents a conductor of a first signal which is internal to the circuit, the second direction being substantially perpendicular to the first direction;

a second wiring pattern which extends in the first direction and represents a conductor of a second signal of the circuit;

configuring the intra-cell wiring pattern so that a first end thereof is located substantially a minimum boundary offset interior to the first side boundary; and

configuring the second wiring pattern as follows:

so that a portion thereof has a first end which extends exterior to the first side boundary by a protrusion length which is substantially greater than the minimum boundary offset; and

so that a gap remains between a second end thereof and the second side boundary, a size of the gap in the second direction being substantially greater than the minimum boundary offset.

16. The method of claim 15 , wherein:

the minimum boundary offset is substantially half of a minimum end-to-end spacing for substantially collinear wiring patterns.

17. The method of claim 15 , further comprising:

substantially filling the gap with a dummy pattern;

configuring the dummy pattern so that a first end thereof substantially abuts a second end of the second wiring pattern; and

further configuring the dummy pattern so that a second end thereof is located substantially the minimum boundary offset interior to the second side boundary.

18. The method of claim 15 , further comprising:

further configuring the intra-cell wiring pattern so that a second end of the intra-cell wiring pattern is located substantially the minimum boundary offset from the second side boundary of the cell.

19. The method of claim 15 , further comprising:

further configuring the intra-cell wiring pattern to leave a gap between a second end of the intra-cell wiring pattern and the second side boundary of the cell, a size of the gap in the second direction being substantially greater than the minimum boundary offset.

20. The method of claim 15 , further comprising:

fabricating, based on the layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor device.