Semiconductor-element-including memory device
View Patent ↗A memory device includes pages each including memory cells arranged in columns in plan view on a substrate, and voltages applied to first and second gate conductor layers and first and second impurity regions in each memory cell are controlled to retain a group of positive holes, generated by an impact ionization phenomenon, inside a semiconductor body. The first and second impurity regions are connected to source and bit lines, the first and second gate conductor layers are connected to word and plate lines, and voltages applied to these lines are controlled to perform a page write operation, a page erase operation, and a page read operation. In the page write operation, the group of positive holes are retained inside the semiconductor body at a first time, and a page write post-processing operation of making a group of excess positive holes disappear is performed at a second time.
1. A semiconductor-element-including memory device that is a memory device in which in plan view on a substrate, a plurality of pages are arranged in a column direction, each of the pages being constituted by a plurality of memory cells arranged in a row direction,
each of the memory cells included in each of the pages comprising:
a semiconductor body that stands on the substrate in a vertical direction or that extends along the substrate in a horizontal direction;
a first impurity region and a second impurity region that are disposed at respective ends of the semiconductor body;
a gate insulator layer that is in contact with a side surface of the semiconductor body between the first impurity region and the second impurity region;
a first gate conductor layer that partially or entirely covers the gate insulator layer; and
a second gate conductor layer that is adjacent to the first gate conductor layer and that is in contact with a side surface of the gate insulator layer, wherein
voltages applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer are controlled to perform a page write operation, a page erase operation, and a page read operation, and
in the page write operation, a group of positive holes generated by an impact ionization phenomenon are retained inside the semiconductor body at a first time, and a page write post-processing operation of making a group of excess positive holes among the group of positive holes disappear is performed at a second time subsequent to the first time.
2. The semiconductor-element-including memory device according to claim 1 , wherein
in the page write operation, a voltage of the semiconductor body is made equal to a first data retention voltage that is higher than a voltage of one of the first impurity region or the second impurity region or higher than voltages of both of the first impurity region and the second impurity region, and
in the page erase operation, the voltages applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer are controlled to make the group of positive holes in the semiconductor body disappear, and the voltage of the semiconductor body is made equal to a second data retention voltage that is lower than the first data retention voltage.
3. The semiconductor-element-including memory device according to claim 1 , wherein
the first impurity region is connected to a source line, the second impurity region is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer is connected to a plate line, and
voltages applied to the source line, the bit line, the word line, and the plate line are controlled to perform the page write operation, the page erase operation, the page read operation, and the page write post-processing operation.
4. The semiconductor-element-including memory device according to claim 3 , wherein
in the page write post-processing operation, a pulse voltage is applied to at least one of the source line, the bit line, the word line, or the plate line.
5. The semiconductor-element-including memory device according to claim 3 , wherein
in the page write post-processing operation, voltages identical to voltages applied in the page read operation are applied to the bit line, the word line, and the plate line.
6. The semiconductor-element-including memory device according to claim 3 , wherein
in the page write post-processing operation, a voltage higher than a voltage applied in the page read operation is applied to at least one of the bit line, the word line, or the plate line.
7. The semiconductor-element-including memory device according to claim 4 , wherein
in the page write post-processing operation, the pulse voltage is applied at least once to a page selected from among the pages.
8. The semiconductor-element-including memory device according to claim 3 , wherein
the word line and the plate line are disposed in parallel in plan view, and
the bit line is disposed in a direction perpendicular to the word line and the plate line in plan view.
9. The semiconductor-element-including memory device according to claim 3 , wherein
a first gate capacitance between the semiconductor body and the first gate conductor layer or the second gate conductor layer to which the plate line is connected is larger than a second gate capacitance between the semiconductor body and the first gate conductor layer or the second gate conductor layer to which the word line is connected.
10. The semiconductor-element-including memory device according to claim 3 , wherein
in plan view, the source line includes isolated source lines that are disposed for respective groups of memory cells arranged in the column direction and that are disposed parallel to the word line and the plate line.
11. The semiconductor-element-including memory device according to claim 3 , wherein
in plan view, the source line is disposed so as to be shared between pages adjacent to each other.
12. The semiconductor-element-including memory device according to claim 3 , wherein
in plan view, the plate line is disposed so as to be shared between at least two or more pages adjacent to each other.
13. The semiconductor-element-including memory device according to claim 1 , wherein
the first gate conductor layer is constituted by two divided gate conductor layers isolated from each other, and the divided gate conductor layers are positioned on respective sides of the second gate conductor layer, and
the page write operation, the page erase operation, the page read operation, and the page write post-processing operation are performed.
14. The semiconductor-element-including memory device according to claim 1 , wherein
the second gate conductor layer is constituted by two divided gate conductor layers isolated from each other, and the divided gate conductor layers are positioned on respective sides of the first gate conductor layer, and
the page write operation, the page erase operation, the page read operation, and the page write post-processing operation are performed.
15. The semiconductor-element-including memory device according to claim 1 , wherein
the semiconductor body is a P-type semiconductor layer, and the first impurity region and the second impurity region are N-type semiconductor layers.
16. The semiconductor-element-including memory device according to claim 1 , wherein
in the page erase operation, selective erasing is performed for at least two pages.
17. The semiconductor-element-including memory device according to claim 3 , wherein
the word line and the plate line are connected to a row decoder circuit, the row decoder circuit receives a row address, and a page is selected from among the pages in accordance with the row address.
18. The semiconductor-element-including memory device according to claim 3 , wherein
the bit line is connected to a sense amplifier circuit, the sense amplifier circuit is connected to a column decoder circuit, the column decoder circuit receives a column address, and the sense amplifier circuit is selectively connected to an input/output circuit in accordance with the column address.