Reduction of middle-of-line resistance and capacitance
A semiconductor structure includes a plurality of vertical transport field effect transistors, and an interconnect structure connected to one of respective source/drain regions of at least two vertical transport field effect transistors of the plurality of vertical transport field effect transistors and respective gate regions of the at least two vertical transport field effect transistors. The interconnect structure comprises a damascene portion, and a subtractive portion disposed on the damascene portion.
1 . A semiconductor structure, comprising:
a plurality of vertical transport field effect transistors; and
an interconnect structure connected to one of respective source/drain regions of at least two vertical transport field effect transistors of the plurality of vertical transport field effect transistors and respective gate regions of the at least two vertical transport field effect transistors, wherein the interconnect structure comprises:
a damascene portion; and
a subtractive portion disposed on a top surface of the damascene portion.
2 . The semiconductor structure of claim 1 , wherein the damascene portion and the subtractive portion comprise the same metal.
3 . The semiconductor structure of claim 1 , wherein the subtractive portion comprises a single metal layer.
4 . The semiconductor structure of claim 3 , wherein the damascene portion comprises a metal fill layer disposed on a liner layer.
5 . The semiconductor structure of claim 4 , wherein the metal fill layer comprises the same metal as the single metal layer.
6 . The semiconductor structure of claim 1 , wherein the damascene portion comprises at least one via, wherein the at least one via is connected to one of the respective source/drain regions and the respective gate regions of the at least two vertical transport field effect transistors.
7 . The semiconductor structure of claim 1 , wherein the damascene portion and the subtractive portion are continuous at one or more junctions between the damascene portion and the subtractive portion.
8 . The semiconductor structure of claim 1 , wherein the subtractive portion increases in width from a top of the subtractive portion to a bottom of the subtractive portion.
9 . The semiconductor structure of claim 8 , wherein the damascene portion decreases in width from a top of the damascene portion to a bottom of the damascene portion.
10 . The semiconductor structure of claim 1 , further comprising a via disposed through the subtractive portion.
11 . The semiconductor structure of claim 1 , further comprising a via disposed on a top surface of the subtractive portion and wrapping around sides of the subtractive portion.
12 . The semiconductor structure of claim 1 , further comprising a via disposed on a top surface of the subtractive portion and extending beyond edges of the subtractive portion.
13 . The semiconductor structure of claim 1 , wherein the respective source/drain regions comprise top source/drain regions of the at least two vertical transport field effect transistors.
14 . The semiconductor structure of claim 1 , wherein the respective source/drain regions comprise a first source/drain region having a first doping type and a second source/drain region having a second doping type different from the first doping type.
15 . The semiconductor structure of claim 1 , wherein:
a length of the damascene portion is at least three times a width of the damascene portion; and
a length of the subtractive portion is at least three times a width of the subtractive portion.
16 . A semiconductor structure, comprising:
a plurality of vertical semiconductor channel regions;
a plurality of source/drain regions, wherein respective ones of the plurality of source/drain regions are disposed on top of respective ones the plurality of vertical semiconductor channel regions; and
an interconnect structure connected to the respective ones of the plurality of source/drain regions, wherein the interconnect structure comprises:
a damascene portion; and
a subtractive portion disposed on a top surface of the damascene portion.
17 . The semiconductor structure of claim 16 , wherein the subtractive portion increases in width from a top of the subtractive portion to a bottom of the subtractive portion.
18 . The semiconductor structure of claim 16 , further comprising a via disposed through the subtractive portion.
19 . The semiconductor structure of claim 16 , wherein the damascene portion comprises at least one via, wherein the at least one via is connected to one of the respective source/drain regions of the respective ones the plurality of vertical semiconductor channel regions.
20 . The semiconductor structure of claim 16 , wherein the damascene portion and the subtractive portion are continuous at one or more junctions between the damascene portion and the subtractive portion.