FinFET complementary metal-oxide-semiconductor (CMOS) devices
A method of fabricating a complementary metal-oxide-semiconductor device is provided. The method includes forming a work function material layer segment on a gate dielectric layer over a first vertical fin and a bottom spacer layer on an n-type bottom source/drain adjoining the first vertical fin on a first region of a substrate, wherein the gate dielectric layer is also over a second vertical fin, bottom spacer layer on a p-type bottom source/drain adjoining the second vertical fin on a second region. The method further includes heat treating the work function material layer segment to produce a modified work function material layer segment on the first vertical fin with a shifted work function value, forming a second work function material layer on the modified work function material layer segment and the gate dielectric layer on the second vertical fin, and growing a top source/drain on each of the vertical fins.
1. A method of fabricating a complementary metal-oxide-semiconductor (CMOS) device, comprising:
forming an n-type bottom source/drain and a p-type bottom source/drain on a substrate;
forming a work function material layer segment on a gate dielectric layer over a first vertical fin and a bottom spacer layer on the n-type bottom source/drain adjoining the first vertical fin on a first region of the substrate, wherein the gate dielectric layer is also over a second vertical fin and the bottom spacer layer on the p-type bottom source/drain adjoining the second vertical fin on a second region of the substrate, and wherein the bottom spacer layer, the gate dielectric layer, and the work function material layer fill a gap between the n-type bottom source/drain and the p-type bottom source/drain;
heat treating the work function material layer segment to produce a modified work function material layer segment on the first vertical fin with a shifted work function value;
forming a second work function material layer on the modified work function material layer segment and the gate dielectric layer on the second vertical fin; and
growing a top source/drain on each of the first vertical fin and the second vertical fin.
2. The method of claim 1 , wherein the heat treating is a spike rapid thermal anneal.
3. The method of claim 2 , wherein the spike rapid thermal anneal has a peak temperature in a range of about 800° C. to about 1100° C.
4. The method of claim 1 , wherein the heat treating is a laser anneal.
5. The method of claim 1 , wherein the work function material layer segment has a thickness in a range of about 3 nm to about 10 nm.
6. The method of claim 1 , wherein the work function material layer segment is a work function material selected from the group consisting of titanium nitride (TiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), and combinations thereof.
7. The method of claim 1 , further comprising forming an isolation region in the substrate between the first vertical fin and the second vertical fin, wherein the gap is over the isolation region.
8. The method of claim 7 , further comprising forming a reduced height fill layer on the second work function material layer.
9. The method of claim 8 , further comprising depositing a top spacer on the reduced height fill layer.
10. A method of fabricating a complementary metal-oxide-semiconductor (CMOS) device, comprising:
forming an n-type bottom source/drain adjoining a first vertical fin on a first region of a substrate and a p-type bottom source/drain adjoining a second vertical fin on a second region of the substrate, wherein there is an isolation region in the substrate between the first vertical fin and the second vertical fin, and a gap between the n-type bottom source/drain and the p-type bottom source/drain above the isolation region;
depositing a bottom spacer layer on the n-type bottom source/drain and p-type bottom source/drain by selective deposition, wherein a portion of the bottom spacer layer is in the gap between the n-type bottom source/drain and the p-type bottom source/drain;
depositing a gate dielectric layer on the bottom spacer layer, first vertical fin, and second vertical fin, wherein a portion of the gate dielectric layer is in the gap;
forming a work function material layer segment on the first vertical fin and in the gap;
heat treating the work function material layer segment to produce a modified work function material layer segment on the first vertical fin with a shifted work function value;
forming a second work function material layer on the modified work function material layer segment and the gate dielectric layer on the second vertical fin; and
growing a top source/drain on each of the first vertical fin and the second vertical fin.
11. The method of claim 10 , further comprising forming a reduced height fill layer on the second work function material layer.
12. The method of claim 11 , wherein the work function material layer segment is a work function material selected from the group consisting of titanium nitride (TiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN titanium carbide (TiC), titanium aluminum carbide (TiAlC), and combinations thereof.
13. The method of claim 12 , wherein the heat treatment is a spike rapid thermal anneal that has a peak temperature in a range of about 800° C. to about 1100° C.
14. The method of claim 12 , wherein the modified work function material layer segment has a work function in a range of about 3.8 electron volts (eV) to about 4.1 eV.
15. The method of claim 14 , wherein the second work function material layer is a work function material selected from the group consisting of titanium nitride (TiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), titanium carbide (TiC), titanium aluminum carbide (TiAlC), and combinations thereof.