Semiconductor test apparatus using FPGA and memory control method for semiconductor test
A semiconductor test apparatus comprises a failure memory (FM) block configured to store failure data generated from a result of testing a semiconductor device, a buffer memory (BM) block to/in which the failure data stored in the FM block is configured to be copied/stored, and a field programmable gate array (FPGA) configured to perform a first control operation to control the FM block and a second control operation to control the BM block.
1 . A semiconductor test apparatus comprising:
a failure memory (FM) block configured to store failure data, which is generated from a result of testing a semiconductor device;
a buffer memory (BM) block to/in which the failure data stored in the FM block is configured to be copied/stored; and
a field programmable gate array (FPGA) configured to perform a first control operation to control the FM block and a second control operation to control the BM block,
wherein the FPGA has a Ping Pong PHY IP configuration.
2 . The semiconductor test apparatus of claim 1 , further comprising:
a printed circuit board (PCB) on which the FPGA, the FM block, and the BM block are mounted.
3 . The semiconductor test apparatus of claim 2 , wherein
each of the FM and BM blocks includes first and second memory groups, and
each of the first and second memory groups includes main and spare memories, which are mounted in top and bottom areas, respectively, of the PCB.
4 . The semiconductor test apparatus of claim 1 , wherein each of the FM and BM blocks includes first and second memory groups, and the FPGA is configured to control the first and second memory groups at an interval of a specific amount of time apart.
5 . The semiconductor test apparatus of claim 1 , wherein
each of the FM and BM blocks includes first and second memory groups, and
the FPGA is configured to transmit first and second control command signals, which are for controlling the first and second memory groups, respectively, during first and third cycles, respectively, of a dynamic random-access memory (DRAM) clock, among four cycles of the DRAM clock that correspond to a first cycle of a user clock.
6 . The semiconductor test apparatus of claim 1 , wherein
each of the FM and BM blocks includes first and second memory groups, and the semiconductor test apparatus further comprises:
a control interface configured to transmit control command signals between the FPGA and the first memory group and between the FPGA and the second memory group.
7 . The semiconductor test apparatus of claim 1 , wherein the BM block is configured to have redundancy analysis performed thereupon.
8 . The semiconductor test apparatus of claim 1 , wherein the FM block is configured to store the failure data in an interleaving manner.
9 . The semiconductor test apparatus of claim 1 , wherein the FM block includes Dynamic Random Access Memory (DRAM).
10 . A memory control method for a semiconductor test, performed by a semiconductor test apparatus, which includes a failure memory (FM) block, a buffer memory (BM) block, and a field programmable gate array (FPGA), the memory control method comprising:
storing, by the FM block, failure data, which is generated from a result of testing a semiconductor device;
copying the failure data to, and storing the failure data in, the BM block; and
performing, by the FPGA, a first control operation for controlling the FM block and a second control operation for controlling the BM block,
wherein the FPGA has a Ping Pong PHY IP configuration.
11 . The memory control method of claim 10 , wherein the semiconductor test apparatus further includes a printed circuit board (PCB) on which the FPGA, the FM block, and the BM block are mounted.
12 . The memory control method of claim 11 , wherein
each of the FM and BM blocks includes first and second memory groups, and
each of the first and second memory groups includes main and spare memories, which are mounted in top and bottom areas, respectively, of the PCB.
13 . The memory control method of claim 11 , wherein
each of the FM and BM blocks includes first and second memory groups, and
the performing the first and second control operations, comprises controlling, by the FPGA, the first and second memory groups at an interval of a predetermined amount of time apart.
14 . The memory control method of claim 11 , wherein
each of the FM and BM blocks includes first and second memory groups, and
the performing the first and second control operations, comprises transmitting, by the FPGA, first and second control command signals, which are for controlling the first and second memory groups, respectively, during first and third cycles, respectively, of a dynamic random-access memory (DRAM) clock, among four cycles of the DRAM clock that correspond to a first cycle of a user clock.
15 . The memory control method of claim 11 , wherein
each of the FM and BM blocks includes first and second memory groups, and
the semiconductor test apparatus further includes a control interface, which transmits control command signals between the FPGA and the first memory group and between the FPGA and the second memory group.
16 . The memory control method of claim 10 , further comprising:
performing a redundancy analysis on the BM block.
17 . The memory control method of claim 10 , wherein the storing, by the FM block, failure data includes storing the failure data in an interleaving manner.
18 . A semiconductor test apparatus comprising:
a failure memory (FM) block configured to store failure data, which is generated from a result of testing a semiconductor device;
a buffer memory (BM) block to/in which the failure data stored in the FM block is configured to be copied/stored;
a field programmable gate array (FPGA) configured to perform a first control operation to control the FM block and a second control operation to control the BM block; and
a printed circuit board (PCB) on which the FPGA, the FM block, and the BM block are mounted, wherein
each of the FM and BM blocks includes first and second memory groups, and
each of the first and second memory groups includes main and spare memories, which are mounted in top and bottom areas, respectively, of the PCB.
19 . The semiconductor test apparatus of claim 18 , wherein
each of the FM and BM blocks includes first and second memory groups, and
each of the first and second memory groups includes main and spare memories, which are mounted in top and bottom areas, respectively, of the PCB.
20 . The semiconductor test apparatus of claim 18 , wherein
each of the FM and BM blocks includes first and second memory groups, and
each of the first and second memory groups includes main and spare memories, which are mounted in top and bottom areas, respectively, of the PCB.