Array substrate, display panel and display device
An array substrate, a display panel and a display device are provided. The array substrate includes: a substrate, a pixel circuit arranged on one side of the substrate and a body part. The pixel circuit includes a driving transistor and a threshold compensation transistor, a first electrode of the threshold compensation transistor is connected to a gate of the driving transistor, and a second electrode of the threshold compensation transistor and a first electrode of the driving transistor are both connected to a connection part. The body part is electrically connected to a power supply voltage signal end. An orthographic projection of the connection part on the substrate at least partially overlaps with an orthographic projection of the body part on the substrate.
1 . An array substrate, comprising:
a substrate;
a pixel circuit arranged on one side of the substrate, wherein the pixel circuit comprises a driving transistor and a threshold compensation transistor, a first electrode of the threshold compensation transistor is connected to a gate of the driving transistor, and a second electrode of the threshold compensation transistor and a first electrode of the driving transistor are both connected to a connection part;
a body part, wherein the body part is electrically connected to a power supply voltage signal end;
wherein an orthographic projection of the connection part on the substrate at least partially overlaps with an orthographic projection of the body part on the substrate;
wherein the pixel circuit further comprises a first reset transistor, a first electrode of the first reset transistor is connected to a first reset signal line, and a second electrode of the first reset transistor is connected to the first electrode of the threshold compensation transistor;
a gate of the first reset transistor is connected to a second scanning line, a gate of the threshold compensation transistor is connected to a third scanning line, the second scanning line provides a second scanning signal, the third scanning line provides a third scanning signal, and a turn-on level of the third scanning signal at least partially overlaps with a turn-on level of the second scanning signal in time.
2 . The array substrate according to claim 1 , wherein
the pixel circuit comprises a first capacitor, a first electrode plate of the first capacitor is connected to the gate of the driving transistor, and a second electrode plate of the first capacitor is connected to a power wire;
at least one of the second electrode plate of the first capacitor and the power wire is the body part.
3 . The array substrate according to claim 2 , wherein
the connection part comprises a first connection part and a second connection part, the first connection part is connected to the first electrode of the driving transistor and the second connection part, and the second connection part is connected to the first electrode of the threshold compensation transistor;
the first connection part and the first electrode of the driving transistor are arranged in a same film layer, and the first connection part and the second connection part are arranged in different film layers.
4 . The array substrate according to claim 3 , wherein
a length of the first connection part in a first direction is greater than or equal to a length of the second connection part in the first direction; or
the first connection part is connected to the second connection part via a first through hole, the second connection part is connected to the first electrode of the threshold compensation transistor via a second through hole, and in the first direction, a distance between the first through hole and the first electrode of the driving transistor is greater than a distance between the first through hole and the second through hole.
5 . The array substrate according to claim 3 , further comprising a branch part, wherein the branch part is connected to the body part, and an orthogonal projection of the branch part on the substrate at least partially overlaps with the orthogonal projection of the connection part on the substrate.
6 . The array substrate according to claim 5 , wherein the branch part comprises a first branch part, the first branch part is connected to the second electrode plate of the first capacitor, and an orthogonal projection of the first branch part on the substrate overlaps with an orthogonal projection of at least one of the first connection part and the second connection part on the substrate.
7 . The array substrate according to claim 6 , wherein the first branch part and the second electrode plate of the first capacitor are arranged in a same film layer.
8 . The array substrate according to claim 5 , wherein the branch part comprises a second branch part, the second branch part is electrically connected to a second electrode of the driving transistor, and an orthogonal projection of the second branch part on the substrate overlaps with an orthogonal projection of at least one of the first connection part and the second connection part on the substrate.
9 . The array substrate according to claim 8 , wherein the second branch part is electrically connected to the second electrode of the driving transistor through the power wire.
10 . The array substrate according to claim 8 , wherein
the threshold compensation transistor is an oxide transistor, and the orthogonal projection of the second branch part on the substrate at least partially overlaps with an orthogonal projection of a channel of the threshold compensation transistor on the substrate; and/or,
the first reset transistor is connected to the gate of the driving transistor, the first reset transistor is an oxide transistor, and an orthogonal projection of at least one of the second branch part and the power wire on the substrate at least partially overlaps with an orthogonal projection of a channel of the first reset transistor on the substrate.
11 . The array substrate according to claim 5 , wherein
the second connection part extends in a first direction, the first direction intersects with a second direction, and a width of the second connection part in the second direction is greater than a width of the first connection part in the second direction; or,
a width of the second connection part in the second direction is greater than a width of the power wire in the second direction; or,
a width of the second connection part in the second direction is greater than a width of a data line in the second direction.
12 . The array substrate according to claim 1 , wherein
the pixel circuit further comprises a data writing transistor, a first electrode of the first reset transistor is connected to a first reset signal line, a second electrode of the first reset transistor is connected to the first electrode of the threshold compensation transistor through a third connection part, a first electrode of the data writing transistor is connected to a data line, and a second electrode of the data writing transistor is connected to a second electrode of the driving transistor;
the data writing transistor is a P-type transistor, and the first reset transistor and the threshold compensation transistor are N-type transistors;
a gate of the data writing transistor is connected to a first scanning line, the first scanning line comprises a third branch part, an orthogonal projection of the third branch part on the substrate at least partially overlaps with an orthogonal projection of the third connection part on the substrate.
13 . The array substrate according to claim 1 , wherein
the pixel circuit further comprises a third reset transistor,
wherein a first electrode of the first reset transistor is connected to a first reset signal line, a second electrode of the first reset transistor is connected to the gate of the driving transistor, a first electrode of the third reset transistor is connected to the first reset signal line, and a second electrode of the third reset transistor is connected to the first electrode of the driving transistor.
14 . The array substrate according to claim 13 , wherein a gate of the first reset transistor and a gate of the third reset transistor are connected to a same second scanning line,
a gate of the threshold compensation transistor is connected to a third scanning line, the second scanning line provides a second scanning signal, the third scanning line provides a third scanning signal, and a turn-on level of the third scanning signal at least partially overlaps or does not overlap with a turn-on level of the second scanning signal in time.
15 . The array substrate according to claim 1 , wherein the pixel circuit comprises a first capacitor and a second capacitor, the first capacitor is connected to the gate of the driving transistor, the second capacitor is connected to the first electrode of the driving transistor, a capacitance value of the first capacitor is C 1 , a capacitance value of the second capacitor is C 2 , and 0.8×C 1 ≤C 2 ≤1.2×C 1 .
16 . An array substrate, comprising
a substrate;
a pixel circuit arranged on one side of the substrate, wherein the pixel circuit comprises a driving transistor and a threshold compensation transistor, a first electrode of the threshold compensation transistor is connected to a gate of the driving transistor, and a second electrode of the threshold compensation transistor and a first electrode of the driving transistor are both connected to a connection part;
a body part, wherein the body part is electrically connected to a power supply voltage signal end;
wherein an orthographic projection of the connection part on the substrate at least partially overlaps with an orthographic projection of the body part on the substrate;
wherein the pixel circuit further comprises a second reset transistor, a first electrode of the second reset transistor is connected to a second reset signal line, and a second electrode of the second reset transistor is connected to a first electrode of a light-emitting element,
the second reset signal line comprises a fourth branch part, and an orthogonal projection of the fourth branch part on the substrate at least partially overlaps with an orthogonal projection of the connection part on the substrate,
wherein the fourth branch part is connected to two adjacent second reset signal lines.
17 . The array substrate according to claim 16 , wherein
the threshold compensation transistor is an oxide transistor, and the orthogonal projection of the fourth branch part on the substrate at least partially overlaps with an orthogonal projection of a channel of the threshold compensation transistor on the substrate.
18 . A display panel, comprising an array substrate, the array substrate comprising:
a substrate;
a pixel circuit arranged on one side of the substrate, wherein the pixel circuit comprises a driving transistor and a threshold compensation transistor, a first electrode of the threshold compensation transistor is connected to a gate of the driving transistor, and a second electrode of the threshold compensation transistor and a first electrode of the driving transistor are both connected to a connection part;
a body part, wherein the body part is electrically connected to a power supply voltage signal end;
wherein an orthographic projection of the connection part on the substrate at least partially overlaps with an orthographic projection of the body part on the substrate;
wherein the pixel circuit further comprises a first reset transistor, a first electrode of the first reset transistor is connected to a first reset signal line, and a second electrode of the first reset transistor is connected to the first electrode of the threshold compensation transistor;
a gate of the first reset transistor is connected to a second scanning line, a gate of the threshold compensation transistor is connected to a third scanning line, the second scanning line provides a second scanning signal, the third scanning line provides a third scanning signal, and a turn-on level of the third scanning signal at least partially overlaps with a turn-on level of the second scanning signal in time.
19 . A display device, comprising a display panel, the display panel comprising an array substrate, and the array substrate comprising:
a substrate;
a pixel circuit arranged on one side of the substrate, wherein the pixel circuit comprises a driving transistor and a threshold compensation transistor, a first electrode of the threshold compensation transistor is connected to a gate of the driving transistor, and a second electrode of the threshold compensation transistor and a first electrode of the driving transistor are both connected to a connection part;
a body part, wherein the body part is electrically connected to a power supply voltage signal end;
wherein an orthographic projection of the connection part on the substrate at least partially overlaps with an orthographic projection of the body part on the substrate;
wherein the pixel circuit further comprises a first reset transistor, a first electrode of the first reset transistor is connected to a first reset signal line, and a second electrode of the first reset transistor is connected to the first electrode of the threshold compensation transistor;
a gate of the first reset transistor is connected to a second scanning line, a gate of the threshold compensation transistor is connected to a third scanning line, the second scanning line provides a second scanning signal, the third scanning line provides a third scanning signal, and a turn-on level of the third scanning signal at least partially overlaps with a turn-on level of the second scanning signal in time.