IP Library › Granted Patent US 12,406,622

Granted Patent B2

US 12,406,622 · App. 18/263,043 · Granted Sep 2, 2025

Pixel driving circuit and driving method thereof, display panel, and display apparatus

Inventors: Ning Cong (Beijing, CN); Li Xiao (Beijing, CN); Haoliang Zheng (Beijing, CN); Can Zhang (Beijing, CN); Minghua Xuan (Beijing, CN); Xiaochuan Chen (Beijing, CN); Can Wang (Beijing, CN); Jinfei Niu (Beijing, CN); Jingjing Zhang (Beijing, CN)

Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.; BOE TECHNOLOGY GROUP CO., LTD.

G09G3/3233 G09G3/32 G09G2300/0842 G09G2300/0852 G09G2300/0861 G09G2310/027 G09G2310/0286 G09G2310/062 G09G2310/08 G09G2320/0233 G09G2330/02 G09G2330/021

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Quick Facts

Patent No.: US 12,406,622
App. No.: 18/263,043
Granted: Sep 2, 2025
Kind: B2

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Abstract

A pixel driving circuit includes a driving sub-circuit and a control sub-circuit. The driving sub-circuit is coupled to a data signal terminal, a scan signal terminal, a first power supply voltage terminal, an enable signal control terminal and an element to be driven, and the driving sub-circuit is configured to, in response to an enable signal, transmit a generated driving signal to the element to be driven, and control a current path transmitting the driving signal to be turned on and off. The control sub-circuit is coupled to the enable signal control terminal, and the control sub-circuit is configured to, in response to a signal received at the control signal terminal, transmit a signal received at a first enable signal terminal or a signal received at a second enable signal terminal to the enable signal control terminal.

Claims (88)

1. A pixel driving circuit, comprising:

a driving sub-circuit coupled to a data signal terminal, a scan signal terminal, a first power supply voltage terminal, an enable signal control terminal and an element to be driven, the driving sub-circuit being configured to, in response to a signal received at the scan signal terminal, write a data signal received at the data signal terminal into the driving sub-circuit; and the driving sub-circuit being further configured to, generate a driving signal according to the written data signal and a first voltage signal received at the first power supply voltage terminal, and in response to an enable signal received at the enable signal control terminal, transmit the driving signal to the element to be driven, and control a current path transmitting the driving signal to be turned on and off; and

a control sub-circuit coupled to a control signal terminal, a first enable signal terminal, a second enable signal terminal and the enable signal control terminal, the control sub-circuit being configured to, in response to a signal received at the control signal terminal, transmit a signal received at the first enable signal terminal to the enable signal control terminal, or transmit a signal received at the second enable signal terminal to the enable signal control terminal;

wherein the driving sub-circuit includes a data writing sub-circuit and a driving signal generating sub-circuit, wherein

the data writing sub-circuit is coupled to the data signal terminal, the scan signal terminal and a second node, and the data writing sub-circuit is configured to, in response to a scan signal received at the scan signal terminal, transmit the data signal received at the data signal terminal to the second node;

the driving signal generating sub-circuit is coupled to the second node, the first power supply voltage terminal, the enable signal control terminal and the element to be driven, and the driving signal generating sub-circuit is configured to, in response to the enable signal received at the enable signal control terminal and a voltage at the second node, generate the driving signal according to the first voltage signal received at the first power supply voltage terminal; and the driving signal generating sub-circuit is further configured to, in response to the enable signal received at the enable signal control terminal, control a current path through which the driving signal is transmitted to the element to be driven to be turned on and off.

2. The pixel driving circuit according to claim 1 , wherein the driving signal generating sub-circuit includes a driving transistor and an enable transistor;

a first electrode of the driving transistor is coupled to the first power supply voltage terminal, a second electrode of the driving transistor is coupled to a first node, and a control electrode of the driving transistor is coupled to the second node;

a first electrode of the enable transistor is coupled to the first node, a second electrode of the enable transistor is coupled to a third node, and a control electrode of the enable transistor is coupled to the enable signal control terminal; and

the third node is further coupled to a first electrode of the element to be driven, and a second electrode of the element to be driven is coupled to a second power supply voltage terminal.

3. The pixel driving circuit according to claim 1 , wherein the data writing sub-circuit includes: a writing transistor, a first capacitor and a first reset transistor;

a first electrode of the writing transistor is coupled to the data signal terminal, a second electrode of the writing transistor is coupled to the second node, and a control electrode of the writing transistor is coupled to the scan signal terminal;

a first electrode of the first reset transistor is coupled to a first node, a second electrode of the first reset transistor is coupled to a reset signal terminal, and a control electrode of the first reset transistor is coupled to the scan signal terminal; and

a first electrode of the first capacitor is coupled to the first node, and a second electrode of the first capacitor is coupled to the second node.

4. The pixel driving circuit according to claim 1 , wherein the data writing sub-circuit includes: a first transmission transistor, a second transmission transistor and a first capacitor, and the scan signal terminal includes a first scan signal terminal and a second scan signal terminal;

a first electrode of the first transmission transistor is coupled to the data signal terminal, a second electrode of the first transmission transistor is coupled to the second node, and a control electrode of the first transmission transistor is coupled to the first scan signal terminal;

a first electrode of the second transmission transistor is coupled to the data signal terminal, a second electrode of the second transmission transistor is coupled to the second node, and a control electrode of the second transmission transistor is coupled to the second scan signal terminal; and

a first electrode of the first capacitor is coupled to the second node, and a second electrode of the first capacitor is coupled to a reference voltage terminal.

5. The pixel driving circuit according to claim 1 , wherein the pixel driving circuit further comprises a reset sub-circuit coupled to a third node, the scan signal terminal and a reset signal terminal; and the reset sub-circuit is configured to, in response to the scan signal received at the scan signal terminal, transmit a reset signal received at the reset signal terminal to the third node; or

the pixel driving circuit further comprises the reset sub-circuit coupled to the third node, the scan signal terminal and the reset signal terminal; the reset sub-circuit is configured to, in response to the scan signal received at the scan signal terminal, transmit the reset signal received at the reset signal terminal to the third node; and the reset sub-circuit includes a second reset transistor; a first electrode of the second reset transistor is coupled to the third node, a second electrode of the second reset transistor is coupled to the reset signal terminal, and a control electrode of the second reset transistor is coupled to the scan signal terminal.

6. The pixel driving circuit according to claim 1 , wherein the control sub-circuit includes a first enable sub-circuit and a second enable sub-circuit,

the second enable sub-circuit is coupled to a fifth node, the second enable signal terminal and the enable signal control terminal, and the second enable sub-circuit is configured to, in response to a second control signal received at the fifth node, transmit a second enable signal received at the second enable signal terminal to the enable signal control terminal.

7. The pixel driving circuit according to claim 6 , wherein the first enable sub-circuit includes a first control transistor; a first electrode of the first control transistor is coupled to the first enable signal terminal, a second electrode of the first control transistor is coupled to the enable signal control terminal, and a control electrode of the first control transistor is coupled to the fourth node; and

the second enable sub-circuit includes a second control transistor; a first electrode of the second control transistor is coupled to the second enable signal terminal, a second electrode of the second control transistor is coupled to the enable signal control terminal, and a control electrode of the second control transistor is coupled to the fifth node.

8. The pixel driving circuit according to claim 6 , wherein transistors included in the first enable sub-circuit and the second enable sub-circuit are of a same conduction type;

the control sub-circuit further includes a first enable control sub-circuit and a second enable control sub-circuit, and the control signal terminal includes a first control signal terminal and a second control signal terminal;

the first enable control sub-circuit is coupled to the fourth node, the first control signal terminal and a first control data signal terminal, and the first enable control sub-circuit is configured to, in response to a first control gate signal received at the first control signal terminal, transmit a signal received at the first control data signal terminal to the fourth node; and

the second enable control sub-circuit is coupled to the fifth node, the second control signal terminal and a second control data signal terminal, and the second enable control sub-circuit is configured to, in response to a second control gate signal received at the second control signal terminal, transmit a signal received at the second control data signal terminal to the fifth node.

9. The pixel driving circuit according to claim 8 , wherein the first enable control sub-circuit includes a first enable control transistor and a second capacitor; a first electrode of the first enable control transistor is coupled to the first control data signal terminal, a second electrode of the first enable control transistor is coupled to the fourth node, and a control electrode of the first enable control transistor is coupled to the first control signal terminal;

a first electrode of the second capacitor is coupled to the fourth node, and a second electrode of the second capacitor is coupled to a first voltage signal terminal;

the second enable control sub-circuit includes a second enable control transistor and a third capacitor; a first electrode of the second enable control transistor is coupled to the second control data signal terminal, a second electrode of the second enable control transistor is coupled to the fifth node, and a control electrode of the second enable control transistor is coupled to the second control signal terminal; and

a first electrode of the third capacitor is coupled to the fifth node, and a second electrode of the third capacitor is coupled to a second voltage signal terminal.

10. The pixel driving circuit according to claim 6 , wherein transistors included in the first enable sub-circuit and the second enable sub-circuit are of opposite conduction types;

the control sub-circuit further includes an enable control sub-circuit and a signal latch circuit; the control signal terminal is a control gate signal terminal;

the enable control sub-circuit is coupled to the control gate signal terminal, a control data signal terminal and the fifth node, and the enable control sub-circuit is configured to, in response to a control gate signal received at the control gate signal terminal, transmit a control data signal received at the control data signal terminal to the fifth node; and

the signal latch circuit is coupled to the fourth node and the fifth node, and the signal latch circuit is configured to transmit the control data signal received at the control data signal terminal to the fourth nodes.

11. The pixel driving circuit according to claim 10 , wherein the enable control sub-circuit includes an enable control transistor; a first electrode of the enable control transistor is coupled to the control data signal terminal, a second electrode of the enable control transistor is coupled to the fifth node and the signal latch circuit, and a control electrode of the enable control transistor is coupled to the control gate signal terminal.

12. The pixel driving circuit according to claim 10 , wherein the signal latch circuit includes a fourth capacitor, a first electrode of the fourth capacitor is coupled to the fourth node and the fifth node, and a second electrode of the fourth capacitor is coupled to a third voltage signal terminal; or

the signal latch circuit includes: a first latch transistor, a second latch transistor, a third latch transistor and a fourth latch transistor; conduction types of the first latch transistor and the fourth latch transistor are opposite to conduction types of the second latch transistor and the third latch transistor;

a first electrode of the first latch transistor is coupled to a fourth voltage signal terminal, a second electrode of the first latch transistor is coupled to the fifth node, and a control electrode of the first latch transistor is coupled to the fourth node;

a first electrode of the second latch transistor is coupled to the fifth node, a second electrode of the second latch transistor is coupled to a first electrode of the third latch transistor, and a control electrode of the second latch transistor is coupled to the fourth node;

a second electrode of the third latch transistor is coupled to the fourth node, and a control electrode of the third latch transistor is coupled to the fifth node; and

a first electrode of the fourth latch transistor is coupled to the fourth node, a second electrode of the fourth latch transistor is coupled to a fifth voltage signal terminal, and a control electrode of the fourth latch transistor is coupled to the fifth node.

13. A display panel, comprising:

the pixel driving circuit according to claim 1 ; and

an element to be driven, the element to be driven being coupled to the pixel driving circuit.

14. The display panel according to claim 13 , wherein

the control sub-circuit includes a first enable sub-circuit and a second enable sub-circuit;

the first enable sub-circuit is coupled to a fourth node, the first enable signal terminal and the enable signal control terminal, and the first enable sub-circuit is configured to, in response to a first control signal received at the fourth node, transmit a first enable signal received at the first enable signal terminal to the enable signal control terminal; and the second enable sub-circuit is coupled to a fifth node, the second enable signal terminal and the enable signal control terminal, and the second enable sub-circuit is configured to, in response to a second control signal received at the fifth node, transmit a second enable signal received at the second enable signal terminal to the enable signal control terminal;

transistors included in the first enable sub-circuit and the second enable sub-circuit are of a same conduction type; the control sub-circuit further includes a first enable control sub-circuit and a second enable control sub-circuit, and the control signal terminal includes a first control signal terminal and a second control signal terminal;

the first enable control sub-circuit is coupled to the fourth node, the first control signal terminal and the first control data signal terminal, and the first enable control sub-circuit is configured to, in response to a first control gate signal received at the first control signal terminal, transmit a signal received at the first control data signal terminal to the fourth node; and the second enable control sub-circuit is coupled to the fifth node, the second control signal terminal and the second control data signal terminal, and the second enable control sub-circuit is configured to, in response to a second control gate signal received at the second control signal terminal, transmit a signal received at the second control data signal terminal to the fifth node;

the display panel further comprises:

a plurality of first signal lines, and first enable signal terminals in a row of pixel driving circuits being coupled to a first signal line in the plurality of first signal lines;

a plurality of second signal lines, and second enable signal terminals in the row of pixel driving circuits being coupled to a second signal line in the plurality of second signal lines;

a plurality of third signal lines, first control signal terminals and second control signal terminals in the row of pixel driving circuits being coupled to a third signal line in the plurality of third signal lines, or the first control signal terminals and the second control signal terminals in the row of pixel driving circuits each being coupled to a corresponding third signal line in the plurality of third signal lines; and

a plurality of fourth signal lines, and first control data signal terminals and second control data signal terminals in a column of pixel driving circuits each being coupled to a fourth signal line in the plurality of fourth signal lines.

15. The display panel according to claim 13 , wherein

the control sub-circuit includes a first enable sub-circuit and a second enable sub-circuit;

the display panel further comprises:

a plurality of first signal lines, and first enable signal terminals in a row of pixel driving circuits being coupled to a first signal line in the plurality of first signal lines;

a plurality of second signal lines, and second enable signal terminals in the row of pixel driving circuits being coupled to a second signal line in the plurality of second signal lines;

a plurality of third signal lines, and first control signal terminals and second control signal terminals in the row of pixel driving circuits each being coupled to a third signal line in the plurality of third signal lines; and

a plurality of fourth signal lines, first control data signal terminals and second control data signal terminals in a column of pixel driving circuits being coupled to a fourth signal line in the plurality of fourth signal lines.

16. The display panel according to claim 13 , wherein

the control sub-circuit includes a first enable sub-circuit and a second enable sub-circuit;

transistors included in the first enable sub-circuit and the second enable sub-circuit are of opposite conduction types; the control sub-circuit further includes an enable control sub-circuit and a signal latch circuit; the control signal terminal is a control gate signal terminal;

the enable control sub-circuit is coupled to the control gate signal terminal, the fifth node and the control data signal terminal, and the enable control sub-circuit is configured to, in response to a control gate signal received at the control gate signal terminal, transmit a control data signal received at the control data signal terminal to the fifth node; and the signal latch circuit is coupled to the fourth node and the fifth node, and the signal latch circuit is configured to transmit the control data signal received at the control data signal terminal to the fourth nodes; and

the display panel further comprises:

a plurality of first signal lines, and first enable signal terminals in a row of pixel driving circuits being coupled to a first signal line in the plurality of first signal lines;

a plurality of second signal lines, and second enable signal terminals in the row of pixel driving circuits being coupled to a second signal line in the plurality of second signal lines;

a plurality of third signal lines, and control data signal terminals in the row of pixel driving circuits being coupled to a third signal line in the plurality of third signal lines; and

a plurality of fourth signal lines, and control gate signal terminals in a column of pixel driving circuits being coupled to a fourth signal line in the plurality of fourth signal lines.

17. A display apparatus, comprising:

the display panel according to claim 13 ; and

a driver chip, the driver chip is coupled to the display panel, and the driver chip is configured to provide signals to the display panel.

18. A driving method of a pixel driving circuit, applied to the pixel driving circuit according to claim 1 , wherein

the control sub-circuit is configured to transmit a first enable signal or a second enable signal to the enable signal control terminal;

the driving method of the pixel driving circuit comprises:

when target luminance of the element to be driven by the pixel driving circuit is greater than first luminance,

transmitting, by the control sub-circuit, the first enable signal to the enable signal control terminal, and the first enable signal being configured to control the current path through which the driving signal is transmitted to the element to be driven to be turned on; and

when the target luminance of the element to be driven by the pixel driving circuit is less than the first luminance,

transmitting, by the control sub-circuit, the second enable signal to the enable signal control terminal; the second enable signal being a pulse signal, and the second enable signal being configured to control the current path through which the driving signal is transmitted to the element to be driven to be turned on and off alternately.

19. The driving method according to claim 18 , wherein a duty ratio of the second enable signal is in a range of 0.2% to 100%, inclusive.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2023

From: CONG, NING; XIAO, LI; ZHENG, HAOLIANG; ZHANG, CAN; XUAN, MINGHUA; CHEN, XIAOCHUAN; WANG, CAN; NIU, JINFEI; ZHANG, JINGJING

To: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.; BOE TECHNOLOGY GROUP CO., LTD.

Reel/Frame 064392/0137 →

Continuity (1)

Related Publication 20250014514A1 · Jan 9, 2025

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