Displays with reduced temperature luminance sensitivity
A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.
1. A display pixel comprising:
a light-emitting diode;
a drive transistor coupled in series with the light-emitting diode;
a first capacitor having a first terminal coupled to a gate terminal of the drive transistor and having a second terminal coupled to an anode of the light-emitting diode;
a second capacitor having a first terminal coupled to a source terminal of the drive transistor and having a second terminal configured to receive an adjustable voltage signal; and
a data loading transistor coupled to the source terminal of the drive transistor and configured to receive the adjustable voltage signal or a scan control signal separate from the adjustable voltage signal.
2. The display pixel of claim 1 , further comprising:
a first gate driver having an output coupled to a gate terminal of the data loading transistor; and
a second gate driver having an output coupled to the second terminal of the second capacitor.
3. The display pixel of claim 2 , further comprising:
a first emission transistor coupled between a power supply line and a drain terminal of the drive transistor;
a second emission transistor coupled between the source terminal of the drive transistor and the anode of the light-emitting diode;
a gate-to-drain transistor coupled between the drain terminal and the gate terminal of the drive transistor; and
an initialization transistor having a first terminal coupled to the anode of the light-emitting diode and a second terminal coupled to an initialization line.
4. The display pixel of claim 3 , wherein the second emission transistor is configured to receive an emission signal and wherein the initialization transistor is configured to receive the emission signal.
5. The display pixel of claim 4 , wherein the first emission transistor is configured to receive an additional emission signal from another display pixel in a different row.
6. The display pixel of claim 3 , wherein:
the drive transistor, the gate-to-drain transistor, the data loading transistor, and the initialization transistor comprise semiconducting oxide transistors; and
the first emission transistor and the second emission transistor comprise p-type silicon transistors.
7. The display pixel of claim 1 , further comprising:
a gate driver having an output coupled to the second terminal of the second capacitor and coupled to a gate terminal of the data loading transistor.
8. The display pixel of claim 7 , further comprising:
a first emission transistor coupled between a power supply line and a drain terminal of the drive transistor;
a second emission transistor coupled between the source terminal of the drive transistor and the anode of the light-emitting diode;
a gate-to-drain transistor coupled between the drain terminal and the gate terminal of the drive transistor; and
an initialization transistor having a first terminal coupled to the anode of the light-emitting diode and a second terminal coupled to an initialization line.
9. The display pixel of claim 8 , wherein the drive transistor comprises an n-type silicon transistor and wherein the data loading transistor comprises a semiconducting oxide transistor.
10. The display pixel of claim 9 , wherein the gate-to-drain transistor comprises an n-type silicon transistor.
11. The display pixel of claim 1 , further comprising:
a first emission transistor coupled between a power supply line and a drain terminal of the drive transistor;
a second emission transistor coupled between the source terminal of the drive transistor and the anode of the light-emitting diode;
a gate-to-drain transistor coupled between the drain terminal and the gate terminal of the drive transistor; and
an initialization transistor having a first terminal coupled to the anode of the light-emitting diode and a second terminal coupled to an initialization line.
12. The display pixel of claim 11 , wherein:
the drive transistor, the gate-to-drain transistor, the data loading transistor, and the initialization transistor comprise semiconducting oxide transistors; and
the first emission transistor and the second emission transistor comprise p-type silicon transistors.
13. The display pixel of claim 1 , wherein the data loading transistor is configured to receive the adjustable voltage signal via a first row line, and wherein the second capacitor is configured to receive the adjustable voltage signal via a second row line separate from the first row line.
14. The display pixel of claim 1 , wherein the data loading transistor is configured to receive the adjustable voltage signal via a row line, and wherein the second capacitor is configured to receive the adjustable voltage signal via the row line.
15. A display pixel comprising:
a light-emitting diode;
a drive transistor coupled in series with the light-emitting diode;
a first emission transistor coupled between a power supply line and a first source-drain terminal of the drive transistor;
a second emission transistor coupled between a second source-drain terminal of the drive transistor and an anode of the light-emitting diode and configured to receive an emission signal;
a gate-to-drain transistor coupled between a gate terminal and the first source-drain terminal of the drive transistor;
a data loading transistor coupled to the second source-drain terminal of the drive transistor;
an initialization transistor coupled to the anode terminal of the light-emitting diode and configured to receive the emission signal;
a first capacitor having a first terminal coupled to the gate terminal of the drive transistor and having a second terminal coupled to the anode of the light-emitting diode; and
a second capacitor having a first terminal coupled to the second source-drain terminal of the drive transistor and having a second terminal configured to receive a control voltage via a row line.