Displays with reduced temperature luminance sensitivity
A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.
1. A display, comprising:
gate driver circuitry; and
a plurality of pixels coupled to the gate driver circuitry, wherein at least one pixel in the plurality of pixels comprises:
a drive transistor having a gate terminal, a first source-drain terminal, and a second source-drain terminal;
a gate-to-drain transistor having a first source-drain terminal coupled to the first source-drain terminal of the drive transistor, a second source-drain terminal coupled to the gate terminal of the drive transistor, and a gate terminal configured to receive a first scan signal from the gate driver circuitry;
a light-emitting diode having a first electrode coupled to the second source-drain terminal of the drive transistor and having a second electrode coupled to a power supply line;
a storage capacitor having a first terminal coupled to the gate terminal of the drive transistor and having a second terminal coupled to the first electrode of the light-emitting diode; and
a data loading transistor having a first source-drain terminal coupled to a data line, a second source-drain terminal coupled to the second source-drain terminal of the drive transistor, and a gate terminal configured to receive a second scan signal from the gate driver circuitry, wherein the gate driver circuitry is configured to deassert the second scan signal while the first scan signal is asserted, and wherein a gate-to-source voltage of the drive transistor is decreased after deassertion of the second scan signal by discharging the storage capacitor.
2. The display of claim 1 , wherein the at least one pixel further comprises:
a first emission transistor having a first source-drain terminal coupled to an additional power supply line and having a second source-drain terminal coupled to the first source-drain terminal of the drive transistor;
a second emission transistor having a first source-drain terminal coupled to the second source-drain terminal of the drive transistor and having a second source-drain terminal coupled to the first electrode of the light-emitting diode; and
an initialization transistor having a first source-drain terminal coupled to the second terminal of the storage capacitor and having a second source-drain terminal coupled to a voltage line.
3. The display of claim 2 , wherein the at least one pixel further comprises:
an additional capacitor having a first terminal coupled to the second source-drain terminal of the drive transistor and having a second terminal configured to receive a control signal from the gate driver circuitry.
4. The display of claim 3 , wherein:
a first power supply voltage is provided on the power supply line; and
a second supply voltage, greater than the first power supply voltage, is provided on the additional power supply line.
5. The display of claim 3 , wherein:
the second scan signal is generated using a first gate driver in the gate driver circuitry; and
the control signal is generated using a second gate driver, different than the first gate driver, in the gate driver circuitry.
6. The display of claim 1 , wherein the at least one pixel further comprises:
an additional capacitor having a first terminal coupled to the second source-drain terminal of the drive transistor and having a second terminal configured to receive the second scan signal.
7. The display of claim 6 , wherein:
the data loading transistor is configured to receive the second scan signal via a first row line; and
the additional capacitor is configured to receive the second scan signal via a second row line different than the first row line.
8. The display of claim 7 , wherein the first row line and the second row line are connected at a region peripheral to the plurality of pixels.
9. The display of claim 6 , wherein the data loading transistor and the drive transistor have a same channel type.
10. The display of claim 6 , wherein:
the data loading transistor is configured to receive the second scan signal via a row line; and
the additional capacitor is configured to receive the second scan signal via the row line.
11. The display of claim 1 , wherein the at least one pixel comprises at least three semiconducting oxide transistors and three p-type silicon transistors.
12. The display of claim 1 , wherein the at least one pixel comprises at least four semiconducting oxide transistors and two p-type silicon transistors.
13. The display of claim 1 , wherein the at least one pixel comprises at least five semiconducting oxide transistors and one p-type silicon transistors.
14. The display of claim 1 , wherein the at least one pixel comprises at least six semiconducting oxide transistors and no silicon transistors.
15. The display of claim 1 , wherein the at least one pixel comprises only semiconducting oxide transistors and no silicon transistors.
16. The display of claim 1 , wherein the at least one pixel further comprises:
an emission transistor having a first source-drain terminal coupled to the second source-drain terminal of the drive transistor, a second source-drain terminal coupled to the first electrode of the light-emitting diode, and a gate terminal configured to receive an emission signal; and
an initialization transistor having a first source-drain terminal coupled to the first electrode of the light-emitting diode, a second source-drain terminal coupled to a voltage line, and a gate terminal configured to receive the emission signal.
17. The display of claim 1 , wherein the at least one pixel further comprises:
an emission transistor having a first source-drain terminal coupled to the second source-drain terminal of the drive transistor, a second source-drain terminal coupled to the first electrode of the light-emitting diode, and a gate terminal configured to receive an emission signal; and
an initialization transistor having a first source-drain terminal coupled to the first electrode of the light-emitting diode, a second source-drain terminal coupled to a voltage line, and a gate terminal configured to receive an inverted version of the emission signal.
18. A method of operating a display pixel having a light-emitting diode, a drive transistor coupled in series with the light-emitting diode, a gate-to-drain transistor coupled across gate and drain terminals of the drive transistor, a data loading transistor, and a storage capacitor coupled to the gate terminal of the drive transistor, the method comprising:
during a data programming and threshold voltage sampling phase, using the data loading transistor to load data into the display pixel while the gate-to-drain transistor is activated;
deactivating the data loading transistor while the gate-to-drain transistor is activated; and
after deactivating the data loading transistor, reducing a gate-to-source voltage of the drive transistor by discharging the storage capacitor.
19. The method of claim 18 , wherein the display pixel further includes an additional capacitor directly coupled to the drive transistor, the method further comprising:
after deactivating the data loading transistor, applying a control signal to the additional capacitor to discharge the storage capacitor.
20. The method of claim 19 , wherein applying the control signal to the additional capacitor comprises reducing the control signal to discharge the storage capacitor.
21. The method of claim 18 , further comprising:
before the data programming and threshold voltage sampling phase, performing an on-bias stress operation by activating the data loading transistor while the gate-to-drain transistor is deactivated.