Stacked devices with backside contacts
A semiconductor structure includes a stacked device structure containing a first device and a second device over the first device in a stacked configuration. The semiconductor structure further includes a first backside contact connected to the first device and a first backside power line. The semiconductor structure further includes a second backside contact connected to the second device and a second backside power line.
1 . A semiconductor structure, comprising:
a first stacked device structure comprising a first device and a second device over the first device in a stacked configuration,
a first backside contact connected to the first device and a first backside power line;
a second backside contact connected to the second device and a second backside power line; and
a second stacked device structure adjacent the first stacked device structure and comprising a third device and a fourth device over the third device in a stacked configuration;
wherein the first backside contact is connected to the third device and the first backside power line.
2 . The semiconductor structure of claim 1 , wherein the first device has a first width and the second device has a second width greater than the first width.
3 . The semiconductor structure of claim 1 , wherein the first backside contact has a first height and the second backside contact has a second height greater than the first height.
4 . The semiconductor structure of claim 1 , wherein the first device has a first width and the second device has a second width greater than the first width, and wherein the first backside contact has a first height and the second backside contact has a second height greater than the first height.
5 . The semiconductor structure of claim 1 , wherein the first device and the second device are stacked in a staggard configuration.
6 . The semiconductor structure of claim 5 , further comprising a frontside metal via connecting the first device to a frontside back-end-of-line interconnect.
7 . The semiconductor structure of claim 1 ,
wherein the second backside contact is connected to the fourth device and the second backside power line.
8 . The semiconductor structure of claim 7 , wherein the first device has a first width and the second device has a second width greater than the first width, and wherein the third device has a third width and the fourth device has a fourth width greater than the third width.
9 . The semiconductor structure of claim 1 , further comprising:
a third backside contact connected to the fourth device and the second backside power line;
wherein the first backside contact is connected to the third device and the first backside power line.
10 . The semiconductor structure of claim 9 , wherein the first device has a first width and the second device has a second width greater than the first width, and wherein the third device has a third width and the fourth device has a fourth width greater than the third width.
11 . The semiconductor structure of claim 1 , further comprising:
a third backside contact connected to the third device and the first backside power line;
wherein the second backside contact is connected to the fourth device and the second backside power line.
12 . An integrated circuit, comprising:
one or more semiconductor structures, wherein at least one of the one or more semiconductor structures comprises:
a first stacked device structure comprising a first device and a second device over the first device in a stacked configuration;
a first backside contact connected to the first device and a first backside power line;
a second backside contact connected to the second device and a second backside power line; and
a second stacked device structure adjacent the stacked device structure and comprising a third device and a fourth device over the third device in a stacked configuration;
wherein the first backside contact is connected to the third device and the first backside power line.
13 . The integrated circuit of claim 12 , wherein the first device has a first width and the second device has a second width greater than the first width.
14 . The integrated circuit of claim 13 , wherein the first backside contact has a first height and the second backside contact has a second height greater than the first height.
15 . The integrated circuit of claim 12 , wherein the first device and the second device are stacked in a staggard configuration.
16 . The integrated circuit of claim 15 , wherein the at least one of the one or more semiconductor structures further comprises a frontside metal via connecting the first device to a frontside back-end-of-line interconnect.
17 . The integrated circuit of claim 12 ,
wherein the second backside contact is connected to the fourth device and the second backside power line.
18 . The integrated circuit of claim 12 , wherein the at least one of the one or more semiconductor structures further comprises:
a third backside contact connected to the fourth device and the second backside power line;
wherein the first backside contact is connected to the third device and the first backside power line.
19 . The integrated circuit of claim 12 , wherein the at least one of the one or more semiconductor structures further comprises:
a third backside contact connected to the third device and the first backside power line;
wherein the second backside contact is connected to the fourth device and the second backside power line.
20 . A method, comprising:
forming a second device over a first device in a stacked configuration;
forming a first backside contact connected to the first device;
forming a second backside contact connected to the second device;
forming a first backside power line connected to the first backside contact;
forming a second backside power line connected to the second backside contact; and
forming a fourth device over a third device in a stacked configuration;
wherein the first backside contact is connected to the third device and the first backside power line.